sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

1054

data[0] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA0, 0);

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

1055

data[1] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA1, 0);

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

1056

data[2] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_CMD, 0);

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

1057

data[3] = PACKET0(offset[offset_idx] + UVD_NO_OP, 0);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

444

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0));

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

482

ib->ptr[0] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

484

ib->ptr[2] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

486

ib->ptr[4] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

489

ib->ptr[i] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

178

tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

182

tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

186

tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

191

amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

194

amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

454

amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

456

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

458

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

460

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

463

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

465

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

467

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

492

amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

525

amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0));

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

527

amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

538

amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

174

tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

178

tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

182

tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

187

amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

190

amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

470

amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

472

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

474

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

476

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

479

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

481

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

483

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

508

amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

541

amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

543

amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

545

amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

556

amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1010

amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1013

amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1015

amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1017

amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1042

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1044

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1046

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1055

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1057

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1059

amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1061

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1070

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1072

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1074

amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1076

amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH9, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1078

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1089

amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

492

tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

496

tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

500

tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

505

amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

508

amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

909

amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

911

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

913

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

915

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

918

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

920

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

922

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

977

amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1168

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1171

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1174

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1177

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1181

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1184

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1187

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1244

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1309

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1313

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1316

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1319

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1347

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1350

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1353

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1363

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1366

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1369

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1372

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1399

amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

556

tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

561

tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

566

tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

572

amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

576

amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1300

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1303

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1319

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1339

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1342

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1345

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1348

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1352

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1355

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1358

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1377

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1381

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1384

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1387

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1398

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1401

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1404

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1407

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1432

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1435

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1438

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1993

amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

2110

.nop = PACKET0(0x81ff, 0),

sys/dev/drm/radeon/cik.c

8200

r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));

sys/dev/drm/radeon/evergreen.c

4969

r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));

sys/dev/drm/radeon/ni.c

2069

r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));

sys/dev/drm/radeon/ni.c

2707

radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2), 0));

sys/dev/drm/radeon/ni.c

2711

radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));

sys/dev/drm/radeon/ni.c

2715

radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));

sys/dev/drm/radeon/r100.c

3680

radeon_ring_write(ring, PACKET0(scratch, 0));

sys/dev/drm/radeon/r100.c

3707

radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));

sys/dev/drm/radeon/r100.c

3711

radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));

sys/dev/drm/radeon/r100.c

3735

ib.ptr[0] = PACKET0(scratch, 0);

sys/dev/drm/radeon/r100.c

843

radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));

sys/dev/drm/radeon/r100.c

846

radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));

sys/dev/drm/radeon/r100.c

859

radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));

sys/dev/drm/radeon/r100.c

861

radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));

sys/dev/drm/radeon/r100.c

864

radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));

sys/dev/drm/radeon/r100.c

868

radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));

sys/dev/drm/radeon/r100.c

870

radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));

sys/dev/drm/radeon/r100.c

945

radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));

sys/dev/drm/radeon/r100.c

947

radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));

sys/dev/drm/radeon/r100.c

984

radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));

sys/dev/drm/radeon/r200.c

105

radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));

sys/dev/drm/radeon/r200.c

113

radeon_ring_write(ring, PACKET0(0x720, 2));

sys/dev/drm/radeon/r200.c

120

radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));

sys/dev/drm/radeon/r300.c

212

radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0));

sys/dev/drm/radeon/r300.c

214

radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0));

sys/dev/drm/radeon/r300.c

217

radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));

sys/dev/drm/radeon/r300.c

219

radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));

sys/dev/drm/radeon/r300.c

222

radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));

sys/dev/drm/radeon/r300.c

226

radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));

sys/dev/drm/radeon/r300.c

229

radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));

sys/dev/drm/radeon/r300.c

232

radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));

sys/dev/drm/radeon/r300.c

234

radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));

sys/dev/drm/radeon/r300.c

265

radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));

sys/dev/drm/radeon/r300.c

271

radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0));

sys/dev/drm/radeon/r300.c

273

radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));

sys/dev/drm/radeon/r300.c

277

radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));

sys/dev/drm/radeon/r300.c

279

radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0));

sys/dev/drm/radeon/r300.c

281

radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0));

sys/dev/drm/radeon/r300.c

283

radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));

sys/dev/drm/radeon/r300.c

285

radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));

sys/dev/drm/radeon/r300.c

287

radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));

sys/dev/drm/radeon/r300.c

291

radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0));

sys/dev/drm/radeon/r300.c

293

radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));

sys/dev/drm/radeon/r300.c

295

radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));

sys/dev/drm/radeon/r300.c

297

radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0));

sys/dev/drm/radeon/r300.c

307

radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0));

sys/dev/drm/radeon/r300.c

316

radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0));

sys/dev/drm/radeon/r300.c

318

radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0));

sys/dev/drm/radeon/r300.c

321

radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0));

sys/dev/drm/radeon/r420.c

218

radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1));

sys/dev/drm/radeon/r420.c

234

radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));

sys/dev/drm/radeon/r600.c

2919

radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));

sys/dev/drm/radeon/r600.c

3105

r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));

sys/dev/drm/radeon/radeon_uvd.c

751

ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0);

sys/dev/drm/radeon/radeon_uvd.c

753

ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0);

sys/dev/drm/radeon/radeon_uvd.c

755

ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0);

sys/dev/drm/radeon/radeon_uvd.c

758

ib.ptr[i] = PACKET0(UVD_NO_OP, 0);

sys/dev/drm/radeon/rv515.c

109

radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0));

sys/dev/drm/radeon/rv515.c

118

radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0));

sys/dev/drm/radeon/rv515.c

120

radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0));

sys/dev/drm/radeon/rv515.c

122

radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0));

sys/dev/drm/radeon/rv515.c

124

radeon_ring_write(ring, PACKET0(0x20C8, 0));

sys/dev/drm/radeon/rv515.c

69

radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0));

sys/dev/drm/radeon/rv515.c

75

radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));

sys/dev/drm/radeon/rv515.c

77

radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));

sys/dev/drm/radeon/rv515.c

79

radeon_ring_write(ring, PACKET0(GB_SELECT, 0));

sys/dev/drm/radeon/rv515.c

81

radeon_ring_write(ring, PACKET0(GB_ENABLE, 0));

sys/dev/drm/radeon/rv515.c

83

radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0));

sys/dev/drm/radeon/rv515.c

85

radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0));

sys/dev/drm/radeon/rv515.c

87

radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));

sys/dev/drm/radeon/rv515.c

89

radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));

sys/dev/drm/radeon/rv515.c

91

radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));

sys/dev/drm/radeon/rv515.c

93

radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0));

sys/dev/drm/radeon/rv515.c

95

radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));

sys/dev/drm/radeon/rv515.c

97

radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));

sys/dev/drm/radeon/rv515.c

99

radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0));

sys/dev/drm/radeon/rv770.c

1738

r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));

sys/dev/drm/radeon/si.c

6500

r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));

sys/dev/drm/radeon/uvd_v1_0.c

186

tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);

sys/dev/drm/radeon/uvd_v1_0.c

190

tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);

sys/dev/drm/radeon/uvd_v1_0.c

194

tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);

sys/dev/drm/radeon/uvd_v1_0.c

199

radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0));

sys/dev/drm/radeon/uvd_v1_0.c

202

radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0));

sys/dev/drm/radeon/uvd_v1_0.c

434

radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));

sys/dev/drm/radeon/uvd_v1_0.c

486

radeon_ring_write(ring, PACKET0(UVD_RBC_IB_BASE, 0));

sys/dev/drm/radeon/uvd_v1_0.c

488

radeon_ring_write(ring, PACKET0(UVD_RBC_IB_SIZE, 0));

sys/dev/drm/radeon/uvd_v1_0.c

87

radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));

sys/dev/drm/radeon/uvd_v1_0.c

89

radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));

sys/dev/drm/radeon/uvd_v1_0.c

91

radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));

sys/dev/drm/radeon/uvd_v1_0.c

94

radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));

sys/dev/drm/radeon/uvd_v1_0.c

96

radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));

sys/dev/drm/radeon/uvd_v1_0.c

98

radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));

sys/dev/drm/radeon/uvd_v2_2.c

45

radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));

sys/dev/drm/radeon/uvd_v2_2.c

47

radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));

sys/dev/drm/radeon/uvd_v2_2.c

49

radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));

sys/dev/drm/radeon/uvd_v2_2.c

51

radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));

sys/dev/drm/radeon/uvd_v2_2.c

54

radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));

sys/dev/drm/radeon/uvd_v2_2.c

56

radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));

sys/dev/drm/radeon/uvd_v2_2.c

58

radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));

sys/dev/drm/radeon/uvd_v2_2.c

79

radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));

sys/dev/drm/radeon/uvd_v2_2.c

82

radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));

sys/dev/drm/radeon/uvd_v2_2.c

85

radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));

sys/dev/drm/radeon/uvd_v3_1.c

47

radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));

sys/dev/drm/radeon/uvd_v3_1.c

50

radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));

sys/dev/drm/radeon/uvd_v3_1.c

53

radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));