OUTW
#define OUTONW(r, m) OUTW(r, INW(r) | (m))
#define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m))
OUTW (nc_respid, 1ul<<np->myaddr);/* id to respond to */
OUTW (nc_sien , STO|HTH|MA|SGE|UDC|RST);
OUTW (nc_sien , 0); /* mask all scsi interrupts */
OUTW (nc_sien, RST);
OUTW (nc_respid, 1ul<<np->myaddr); /* Id to respond to */
OUTW (nc_sien , STO|HTH|MA|SGE|UDC|RST|PAR);
OUTW (nc_sien , 0); /* mask all scsi interrupts */
#define OUTONW(r, m) OUTW(r, INW(r) | (m))
#define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m))
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_RISC_DISABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_ENABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, bktr->capcontrol);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_ENABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, bktr->capcontrol);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_ENABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_ENABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, bktr->capcontrol);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_RISC_DISABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_RISC_DISABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_ENABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, bktr->capcontrol);
OUTW(bktr, BKTR_GPIO_DMA_CTL, INW(bktr, BKTR_GPIO_DMA_CTL) & ~FIFO_RISC_ENABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_RISC_DISABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_RISC_DISABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_RISC_DISABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_ENABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, bktr->capcontrol);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_ENABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_RISC_DISABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_RISC_DISABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_RISC_DISABLED);