Symbol: NUM_UCLK_DPM_LEVELS
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1798
while (i < NUM_UCLK_DPM_LEVELS) {
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
3452
return vdd_dep_table_on_mclk->entries[NUM_UCLK_DPM_LEVELS - 1].vddInd + 1;
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
3476
if (data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) {
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
2075
PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2924
PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c
331
for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
sys/dev/drm/amd/powerplay/inc/smu11_driver_if.h
421
uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ];
sys/dev/drm/amd/powerplay/inc/smu11_driver_if.h
55
#define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
sys/dev/drm/amd/powerplay/inc/smu9_driver_if.h
220
uint8_t MemVid[NUM_UCLK_DPM_LEVELS]; /* VID */
sys/dev/drm/amd/powerplay/inc/smu9_driver_if.h
221
PllSetting_t UclkLevel[NUM_UCLK_DPM_LEVELS]; /* Full PLL settings */
sys/dev/drm/amd/powerplay/inc/smu9_driver_if.h
222
uint8_t MemSocVoltageIndex[NUM_UCLK_DPM_LEVELS];
sys/dev/drm/amd/powerplay/inc/smu9_driver_if.h
50
#define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
sys/dev/drm/amd/powerplay/inc/vega12/smu9_driver_if.h
312
uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ];
sys/dev/drm/amd/powerplay/inc/vega12/smu9_driver_if.h
53
#define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)