MMSCH_V1_0_INSERT_DIRECT_WT

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

813

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

815

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

819

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

821

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

826

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

828

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

830

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

832

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

834

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

835

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

837

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

839

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

841

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

842

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

845

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

862

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

873

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

882

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

886

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

902

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

906

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

907

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

908

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

911

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

233

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

235

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

237

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

241

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL), 0x398000);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

243

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL), 0);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

244

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL1), 0);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

245

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0);