sys/dev/drm/amd/amdgpu/uvd_v7_0.c

809

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

849

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

853

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

857

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

890

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

895

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

914

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

242

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CACHE_CTRL), ~0x1, 0);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

293

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), ~0x100, 0);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

294

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

299

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

301

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

303

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

311

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),