MI_LOAD_REGISTER_IMM
if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) &&
CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
*cs++ = MI_LOAD_REGISTER_IMM(4);
*batch++ = MI_LOAD_REGISTER_IMM(1);
*batch++ = MI_LOAD_REGISTER_IMM(count);
*cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds);
regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
*cs++ = MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES);
*cs++ = MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2);
*cs++ = MI_LOAD_REGISTER_IMM(1);
*cs++ = MI_LOAD_REGISTER_IMM(1);
*cs++ = MI_LOAD_REGISTER_IMM(num_rings);
*cs++ = MI_LOAD_REGISTER_IMM(num_rings);
*cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4);
*cs++ = MI_LOAD_REGISTER_IMM(1);
*cs++ = MI_LOAD_REGISTER_IMM(w->count);