Symbol: MI_INSTR
sys/dev/drm/i915/intel_gpu_commands.h
105
#define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */
sys/dev/drm/i915/intel_gpu_commands.h
107
#define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */
sys/dev/drm/i915/intel_gpu_commands.h
110
#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
sys/dev/drm/i915/intel_gpu_commands.h
111
#define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2)
sys/dev/drm/i915/intel_gpu_commands.h
114
#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
sys/dev/drm/i915/intel_gpu_commands.h
123
#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
sys/dev/drm/i915/intel_gpu_commands.h
125
#define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1)
sys/dev/drm/i915/intel_gpu_commands.h
126
#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
sys/dev/drm/i915/intel_gpu_commands.h
128
#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
sys/dev/drm/i915/intel_gpu_commands.h
137
#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 1)
sys/dev/drm/i915/intel_gpu_commands.h
138
#define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2)
sys/dev/drm/i915/intel_gpu_commands.h
139
#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
sys/dev/drm/i915/intel_gpu_commands.h
145
#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
sys/dev/drm/i915/intel_gpu_commands.h
147
#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
sys/dev/drm/i915/intel_gpu_commands.h
226
#define MI_SET_PREDICATE MI_INSTR(0x01, 0)
sys/dev/drm/i915/intel_gpu_commands.h
227
#define MI_ARB_CHECK MI_INSTR(0x05, 0)
sys/dev/drm/i915/intel_gpu_commands.h
228
#define MI_RS_CONTROL MI_INSTR(0x06, 0)
sys/dev/drm/i915/intel_gpu_commands.h
229
#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
sys/dev/drm/i915/intel_gpu_commands.h
230
#define MI_PREDICATE MI_INSTR(0x0C, 0)
sys/dev/drm/i915/intel_gpu_commands.h
231
#define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
sys/dev/drm/i915/intel_gpu_commands.h
232
#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
sys/dev/drm/i915/intel_gpu_commands.h
233
#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
sys/dev/drm/i915/intel_gpu_commands.h
234
#define MI_URB_CLEAR MI_INSTR(0x19, 0)
sys/dev/drm/i915/intel_gpu_commands.h
235
#define MI_UPDATE_GTT MI_INSTR(0x23, 0)
sys/dev/drm/i915/intel_gpu_commands.h
236
#define MI_CLFLUSH MI_INSTR(0x27, 0)
sys/dev/drm/i915/intel_gpu_commands.h
237
#define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0)
sys/dev/drm/i915/intel_gpu_commands.h
239
#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
sys/dev/drm/i915/intel_gpu_commands.h
240
#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
sys/dev/drm/i915/intel_gpu_commands.h
241
#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
sys/dev/drm/i915/intel_gpu_commands.h
242
#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
sys/dev/drm/i915/intel_gpu_commands.h
243
#define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
sys/dev/drm/i915/intel_gpu_commands.h
30
#define MI_NOOP MI_INSTR(0, 0)
sys/dev/drm/i915/intel_gpu_commands.h
31
#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
sys/dev/drm/i915/intel_gpu_commands.h
32
#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
sys/dev/drm/i915/intel_gpu_commands.h
37
#define MI_FLUSH MI_INSTR(0x04, 0)
sys/dev/drm/i915/intel_gpu_commands.h
44
#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
sys/dev/drm/i915/intel_gpu_commands.h
45
#define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
sys/dev/drm/i915/intel_gpu_commands.h
48
#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
sys/dev/drm/i915/intel_gpu_commands.h
49
#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
sys/dev/drm/i915/intel_gpu_commands.h
51
#define MI_SET_APPID MI_INSTR(0x0e, 0)
sys/dev/drm/i915/intel_gpu_commands.h
52
#define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
sys/dev/drm/i915/intel_gpu_commands.h
56
#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
sys/dev/drm/i915/intel_gpu_commands.h
57
#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
sys/dev/drm/i915/intel_gpu_commands.h
58
#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
sys/dev/drm/i915/intel_gpu_commands.h
77
#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */
sys/dev/drm/i915/intel_gpu_commands.h
96
#define MI_SET_CONTEXT MI_INSTR(0x18, 0)