MFI_WRITE4
MFI_WRITE4(sc, MFI_OMSK, 0x01);
MFI_WRITE4(sc, MFI_ODCR0, 0xFFFFFFFF);
MFI_WRITE4(sc, MFI_OMSK, ~MFI_1078_EIM);
MFI_WRITE4(sc, MFI_ODCR0, 0xFFFFFFFF);
MFI_WRITE4(sc, MFI_OMSK, ~MFI_GEN2_EIM);
MFI_WRITE4(sc, MFI_OMSK, ~0x00000001);
MFI_WRITE4(sc, MFI_OSTS, status);
MFI_WRITE4(sc, MFI_OSTS, status);
MFI_WRITE4(sc, MFI_ODCR0, status);
MFI_WRITE4(sc, MFI_IQP,(bus_add >>3) | frame_cnt);
MFI_WRITE4(sc, MFI_IQPL, (bus_add | frame_cnt << 1) | 1);
MFI_WRITE4(sc, MFI_IQPH, 0x00000000);
MFI_WRITE4(sc, MFI_IQP, (bus_add | frame_cnt << 1) | 1);
MFI_WRITE4(sc, MFI_SKINNY_IDB, MFI_FWINIT_CLEAR_HANDSHAKE);
MFI_WRITE4(sc, MFI_IDB, MFI_FWINIT_CLEAR_HANDSHAKE);
MFI_WRITE4(sc, MFI_SKINNY_IDB, 7);
MFI_WRITE4(sc, MFI_IDB, MFI_FWINIT_READY);
MFI_WRITE4(sc, MFI_SKINNY_IDB, MFI_FWINIT_HOTPLUG);
MFI_WRITE4(sc, MFI_IDB, MFI_FWINIT_HOTPLUG);
MFI_WRITE4(sc, MFI_OSTS, status);
MFI_WRITE4(sc, MFI_ILQP, (req_desc->words & 0xFFFFFFFF));
MFI_WRITE4(sc, MFI_IHQP, (req_desc->words >>0x20));
MFI_WRITE4 (sc, 0x00,MFI_STOP_ADP);
MFI_WRITE4 (sc, MFI_IDB,MFI_STOP_ADP);
MFI_WRITE4(sc, MFI_IQPL, (uint32_t)bus_add);
MFI_WRITE4(sc, MFI_IQPH, (uint32_t)((uint64_t)bus_add >> 32));
MFI_WRITE4(sc, MFI_WSR, 0xF);
MFI_WRITE4(sc, MFI_WSR, 4);
MFI_WRITE4(sc, MFI_WSR, 0xB);
MFI_WRITE4(sc, MFI_WSR, 2);
MFI_WRITE4(sc, MFI_WSR, 7);
MFI_WRITE4(sc, MFI_WSR, 0xD);
MFI_WRITE4(sc, MFI_HDR, (HostDiag | DIAG_RESET_ADAPTER));
MFI_WRITE4(sc, MFI_RPI, sc->last_reply_idx);
MFI_WRITE4(sc, MFI_RPI, sc->last_reply_idx);
MFI_WRITE4(sc, MFI_OMSK, ~MFI_FUSION_ENABLE_INTERRUPT_MASK);
MFI_WRITE4(sc, MFI_OMSK, 0xFFFFFFFF);