Symbol: MC_VM_MX_L1_TLB_CNTL
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
116
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
117
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
118
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
120
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
122
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
123
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
125
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
296
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
298
MC_VM_MX_L1_TLB_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
621
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
622
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
623
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
624
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
625
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
742
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
743
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
744
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
848
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
849
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
850
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
851
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
852
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
986
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
987
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
988
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
136
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
137
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
138
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
140
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
142
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
143
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
145
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
328
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
330
MC_VM_MX_L1_TLB_CNTL,
sys/dev/drm/radeon/cik.c
5457
WREG32(MC_VM_MX_L1_TLB_CNTL,
sys/dev/drm/radeon/cik.c
5579
WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
sys/dev/drm/radeon/ni.c
1296
WREG32(MC_VM_MX_L1_TLB_CNTL,
sys/dev/drm/radeon/ni.c
1381
WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
sys/dev/drm/radeon/si.c
4283
WREG32(MC_VM_MX_L1_TLB_CNTL,
sys/dev/drm/radeon/si.c
4376
WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |