MAX_REGULAR_DPM_NUMBER
for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
struct smu10_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER];
MAX_REGULAR_DPM_NUMBER);
MAX_REGULAR_DPM_NUMBER);
SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER);
MAX_REGULAR_DPM_NUMBER);
SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER);
MAX_REGULAR_DPM_NUMBER);
struct smu7_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER];
while (i < MAX_REGULAR_DPM_NUMBER) {
if (table->count <= MAX_REGULAR_DPM_NUMBER) {
return MAX_REGULAR_DPM_NUMBER - 1;
struct vega10_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
struct vega10_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER];
struct phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER];
struct phm_ppt_v1_voltage_lookup_record entries[MAX_REGULAR_DPM_NUMBER];
PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
return MAX_REGULAR_DPM_NUMBER - 1);
struct vega12_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
uint32_t entries[MAX_REGULAR_DPM_NUMBER];
struct vega12_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER];
entries[MAX_REGULAR_DPM_NUMBER];
PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
return MAX_REGULAR_DPM_NUMBER - 1);
struct vega20_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
uint32_t entries[MAX_REGULAR_DPM_NUMBER];
struct vega20_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER];
entries[MAX_REGULAR_DPM_NUMBER];
for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];