MASK
if (which != MASK)
struct sockaddr_in *min = sintab[MASK];
if (which != MASK)
if (which != MASK)
in6_getprefix(p + 1, MASK);
afp->af_getprefix(addr, MASK);
afp->af_getaddr(addr, MASK);
return (minor(dev) & MASK(VINUM_VOL_WIDTH)) >> VINUM_VOL_SHIFT;
return VOL[Volno(dev)].plex[(minor(dev) >> VINUM_PLEX_SHIFT) & (MASK(VINUM_PLEX_WIDTH))];
return ((minor(dev) & MASK(VINUM_VOL_WIDTH)) >> VINUM_VOL_SHIFT) /* low order 8 bits */
& (MASK(VINUM_RAWPLEX_WIDTH)
return PLEX[Plexno(dev)].sdnos[(minor(dev) >> VINUM_SD_SHIFT) & (MASK(VINUM_SD_WIDTH))];
return ((minor(dev) & MASK(VINUM_VOL_WIDTH)) >> VINUM_VOL_SHIFT) /* low order 8 bits */
|((minor(dev) >> VINUM_RAWPLEX_SHIFT) & (MASK(VINUM_RAWPLEX_WIDTH)
SCR_JUMP ^ IFFALSE (MASK (CATN, CATN)),
SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)),
/*<<<*/ SCR_JUMPR ^ IFTRUE (MASK (SCSI_STATUS_SENSE, SCSI_STATUS_SENSE)),
/*<<<*/ SCR_JUMPR ^ IFFALSE (MASK (0, HS_DONEMASK)),
SCR_INT_FLY ^ IFFALSE (MASK (0, HS_DONEMASK)),
/*<<<*/ SCR_JUMPR ^ IFFALSE (MASK (QUIRK_AUTOSAVE, QUIRK_AUTOSAVE)),
SCR_JUMP ^ IFTRUE (MASK (CSIGP,CSIGP)),
SCR_JUMP ^ IFTRUE (MASK (CSIGP,CSIGP)),
/*<<<*/ SCR_JUMPR ^ IFFALSE (MASK (MSG_IDENTIFYFLAG, 0x98)),
SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)),
/*<<<*/ SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)),
SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)),
SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)),
SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)),
SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)),
SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)),
SCR_JUMP ^ IFTRUE (MASK (QUIRK_NOMSG, QUIRK_NOMSG)),
SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)),
SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)),
SCR_JUMP ^ IFTRUE (MASK (0x00, 0xf0)),
SCR_JUMP ^ IFTRUE (MASK (0x10, 0xf0)),
SCR_JUMP ^ IFFALSE (MASK (0x20, 0xf0)),
SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)),
SCR_INT ^ IFTRUE (MASK (SEM, SEM)),
SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)),
SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)),
SCR_JUMP ^ IFFALSE (MASK (WSR, WSR)),
SCR_JUMP ^ IFFALSE (MASK (WSS, WSS)),
SCR_JUMP ^ IFTRUE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))),
SCR_JUMP ^ IFFALSE (MASK (SYM_QUIRK_AUTOSAVE, SYM_QUIRK_AUTOSAVE)),
SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)),
SCR_INT ^ IFFALSE (MASK (0x80, 0x80)),
SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)),
SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)),
SCR_JUMP ^ IFTRUE (MASK (0x00, 0xf0)),
SCR_JUMP ^ IFTRUE (MASK (0x10, 0xf0)),
SCR_JUMP ^ IFFALSE (MASK (0x20, 0xf0)),
SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)),
SCR_JUMP ^ IFTRUE (MASK (0, (HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED))),
SCR_JUMPR ^ IFFALSE (MASK (HF_DP_SAVED, HF_DP_SAVED)),
SCR_JUMP ^ IFTRUE (MASK (0, (HF_IN_PM0 | HF_IN_PM1))),
SCR_JUMPR ^ IFFALSE (MASK (HF_IN_PM0, HF_IN_PM0)),
SCR_JUMP ^ IFTRUE (MASK (HF_ACT_PM, HF_ACT_PM)),
SCR_CALL ^ IFTRUE (MASK (WSR, WSR)),
SCR_CALL ^ IFTRUE (MASK (WSR, WSR)),
SCR_INT ^ IFTRUE (MASK (SEM, SEM)),
SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)),
SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)),
SCR_JUMP ^ IFFALSE (MASK (WSR, WSR)),
SCR_JUMP ^ IFFALSE (MASK (WSS, WSS)),
SCR_JUMPR ^ IFTRUE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))),
SCR_JUMP ^ IFFALSE (MASK (SYM_QUIRK_AUTOSAVE, SYM_QUIRK_AUTOSAVE)),
SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)),
SCR_INT ^ IFFALSE (MASK (0x80, 0x80)),
DDC_GPIO_REG_LIST_ENTRY(MASK,cd,id),\
DDC_GPIO_VGA_REG_LIST_ENTRY(MASK,cd),\
DDC_GPIO_I2C_REG_LIST_ENTRY(MASK,cd),\
HPD_GPIO_REG_LIST_ENTRY(MASK,cd,id),\
REG_UPDATE(MASK_reg, MASK, 1);
REG_UPDATE(MASK_reg, MASK, 1);
REG_UPDATE(MASK_reg, MASK, 1);
REG_UPDATE(MASK_reg, MASK, 0);
REG_UPDATE(MASK_reg, MASK, 0);
REG_GET(MASK_reg, MASK, &gpio->store.mask);
REG_UPDATE(MASK_reg, MASK, gpio->store.mask);
return (id >> p->height) & MASK;
return id & MASK;
idx = p->prefix >> (above - SHIFT) & MASK;
#define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \
pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE)
#define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \
pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE)
return (minor(dev) & MASK(VINUM_VOL_WIDTH)) >> VINUM_VOL_SHIFT;
return VOL[Volno(dev)].plex[(minor(dev) >> VINUM_PLEX_SHIFT) & (MASK(VINUM_PLEX_WIDTH))];
return ((minor(dev) & MASK(VINUM_VOL_WIDTH)) >> VINUM_VOL_SHIFT) /* low order 8 bits */
& (MASK(VINUM_RAWPLEX_WIDTH)
return PLEX[Plexno(dev)].sdnos[(minor(dev) >> VINUM_SD_SHIFT) & (MASK(VINUM_SD_WIDTH))];
return ((minor(dev) & MASK(VINUM_VOL_WIDTH)) >> VINUM_VOL_SHIFT) /* low order 8 bits */
|((minor(dev) >> VINUM_RAWPLEX_SHIFT) & (MASK(VINUM_RAWPLEX_WIDTH)
mask = MASK(s->cmp_num_entries_log2);
mask = MASK(s->msg_num_entries_log2);
e = ring + (s->req_prod_idx & MASK(req_num_entries_log2));
#define PVSCSI_INTR_CMPL_MASK MASK(2)
#define PVSCSI_INTR_MSG_MASK (MASK(2) << 2)
#define PVSCSI_INTR_ALL_SUPPORTED MASK(4)
#define PVSCSI_FLAG_RESERVED_MASK (~MASK(5))
iptr = &ibaa->IBAA_memory[ibaa->memIndex & MASK];
current->protection & MASK(current));
nr1 = deck[n1]&MASK;
nr2 = deck[nr1]&MASK;
i = t2[(t3[(t1[(i+nr1)&MASK]+nr2)&MASK]-nr2)&MASK]-nr1;
ic = (rnd&MASK)%(k+1);
ic = (rnd&MASK)%(k+1);
ic = (rnd&MASK) % k;
t2[t1[i]&MASK] = i;