sys/dev/drm/amd/amdgpu/dce_v10_0.c

2959

lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2965

lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2988

lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2994

lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3085

lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3091

lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3114

lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3120

lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,

sys/dev/drm/radeon/cik.c

6908

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

6909

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

6911

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

6912

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

6915

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

6916

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

7260

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);

sys/dev/drm/radeon/cik.c

7261

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);

sys/dev/drm/radeon/cik.c

7263

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);

sys/dev/drm/radeon/cik.c

7264

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);

sys/dev/drm/radeon/cik.c

7267

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);

sys/dev/drm/radeon/cik.c

7268

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);