sys/dev/netif/ath/ath_hal/ar5211/ar5211_reset.c

478

OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4,

sys/dev/netif/ath/ath_hal/ar5211/ar5211_reset.c

661

!(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_IQCAL)) {

sys/dev/netif/ath/ath_hal/ar5211/ar5211_reset.c

699

data = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) |

sys/dev/netif/ath/ath_hal/ar5211/ar5211_reset.c

703

OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, data);

sys/dev/netif/ath/ath_hal/ar5212/ar5212_reset.c

1001

!(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_IQCAL)) {

sys/dev/netif/ath/ath_hal/ar5212/ar5212_reset.c

1018

OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,

sys/dev/netif/ath/ath_hal/ar5212/ar5212_reset.c

1057

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,

sys/dev/netif/ath/ath_hal/ar5212/ar5212_reset.c

1059

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,

sys/dev/netif/ath/ath_hal/ar5212/ar5212_reset.c

1061

OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,

sys/dev/netif/ath/ath_hal/ar5212/ar5212_reset.c

1076

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,

sys/dev/netif/ath/ath_hal/ar5212/ar5212_reset.c

1079

OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,

sys/dev/netif/ath/ath_hal/ar5212/ar5212_reset.c

1721

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,

sys/dev/netif/ath/ath_hal/ar5212/ar5212_reset.c

1723

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,

sys/dev/netif/ath/ath_hal/ar5212/ar5212_reset.c

1725

OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,

sys/dev/netif/ath/ath_hal/ar5212/ar5212_reset.c

1805

if (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER) {

sys/dev/netif/ath/ath_hal/ar5212/ar5212_reset.c

1808

val = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4);

sys/dev/netif/ath/ath_hal/ar5212/ar5212_reset.c

1896

val = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4);

sys/dev/netif/ath/ath_hal/ar5212/ar5212_reset.c

1900

OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, val);

sys/dev/netif/ath/ath_hal/ar5212/ar5212_reset.c

543

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,

sys/dev/netif/ath/ath_hal/ar5212/ar5212_reset.c

546

OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,

sys/dev/netif/ath/ath_hal/ar5312/ar5312_reset.c

467

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,

sys/dev/netif/ath/ath_hal/ar5312/ar5312_reset.c

470

OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,

sys/dev/netif/ath/ath_hal/ar5416/ar5416_cal.c

100

OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,

sys/dev/netif/ath/ath_hal/ar5416/ar5416_cal.c

128

OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, AR_PHY_TIMING_CTRL4_DO_CAL);

sys/dev/netif/ath/ath_hal/ar5416/ar5416_cal.c

172

if (!ath_hal_wait(ah, AR_PHY_TIMING_CTRL4, AR_PHY_TIMING_CTRL4_DO_CAL, 0)) {

sys/dev/netif/ath/ath_hal/ar5416/ar5416_cal.c

403

if (!(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_CAL)) {

sys/dev/netif/ath/ath_hal/ar5416/ar5416_cal_iq.c

130

OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,

sys/dev/netif/ath/ath_hal/ar5416/ar5416_reset.c

1633

OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4 + regChainOffset,

sys/dev/netif/ath/ath_hal/ar5416/ar5416_reset.c

1634

(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4 + regChainOffset) &

sys/dev/netif/ath/ath_hal/ar5416/ar5416phy.h

146

(AR_PHY_TIMING_CTRL4 + ((_i) << 12))

tools/tools/ath/common/dumpregs_5211.c

274

DEFVOID(AR_PHY_TIMING_CTRL4,"PHY_TIMING_CTRL4"),

tools/tools/ath/common/dumpregs_5212.c

373

DEFVOID(AR_PHY_TIMING_CTRL4,"PHY_TIMING_CTRL4"),