AR_PHY_BASE
OS_REG_WRITE(ah, (AR_PHY_BASE + (0x34 << 2)), 0x00001c16);
OS_REG_WRITE(ah, (AR_PHY_BASE + (0x20 << 2)), 0x00010000);
revid = (OS_REG_READ(ah, AR_PHY_BASE + (256 << 2)) >> 28) & 0xf;
nf = (OS_REG_READ(ah, AR_PHY_BASE + (25 << 2)) >> 19) & 0x1ff;
#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
OS_REG_WRITE(ah, (AR_PHY_BASE + (0x34 << 2)), 0x00001c16);
OS_REG_WRITE(ah, (AR_PHY_BASE + (0x20 << 2)), 0x00010000);
val = (OS_REG_READ(ah, AR_PHY_BASE + (256 << 2)) >> 24) & 0xff;
OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007);
OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000047);
OS_REG_WRITE(ah, AR_PHY_BASE, 0x00004007);
OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007);
uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };
OS_REG_SET_BIT(ah, AR_PHY_BASE, 0x00002000);
OS_REG_WRITE(ah, AR_PHY_BASE + (90 << 2),
OS_REG_WRITE(ah, AR_PHY_BASE + (17 << 2),
(OS_REG_READ(ah, AR_PHY_BASE + (17 << 2)) & 0xFFFFC07F) |
OS_REG_WRITE(ah, AR_PHY_BASE + (18 << 2),
(OS_REG_READ(ah, AR_PHY_BASE + (18 << 2)) & 0xFFFC0FFF) |
OS_REG_WRITE(ah, AR_PHY_BASE + (20 << 2),
(OS_REG_READ(ah, AR_PHY_BASE + (20 << 2)) & 0xFFFF0000) |
OS_REG_WRITE(ah, AR_PHY_BASE + (13 << 2),
OS_REG_WRITE(ah, AR_PHY_BASE + (10 << 2),
(OS_REG_READ(ah, AR_PHY_BASE + (10 << 2)) & 0xFFFF00FF) |
OS_REG_WRITE(ah, AR_PHY_BASE + (25 << 2),
(OS_REG_READ(ah, AR_PHY_BASE + (25 << 2)) & 0xFFF80FFF) |
addr = AR_PHY_BASE + (608 << 2);
OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007);
OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000047);
#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };
#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
} else if (AR_PHY_BASE <= r->reg) {
(r->reg - AR_PHY_BASE) >> 2, r->reg);