IS_GEN9_LP
dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
if (IS_GEN9_LP(dev_priv))
if (IS_GEN9_LP(dev_priv)) {
if (IS_GEN9_LP(dev_priv)) {
if (IS_GEN9_LP(dev_priv)) {
else if (IS_GEN9_LP(dev_priv))
if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
if (IS_GEN9_LP(dev_priv)) {
if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
if (IS_GEN9_LP(dev_priv))
if (IS_GEN9_LP(dev_priv))
} else if (IS_GEN9_LP(dev_priv)) {
if (IS_GEN9_LP(dev_priv))
(IS_GEN9_LP(dev_priv) ? \
(IS_GEN9_LP(dev_priv) ? \
if (WARN_ON_ONCE(!IS_GEN9_LP(dev_priv)))
} else if (IS_GEN9_LP(dev_priv)) {
else if (IS_GEN9_LP(dev_priv))
if (IS_GEN9_LP(dev_priv))
else if (IS_GEN9_LP(dev_priv))
if (ret && IS_GEN9_LP(dev_priv)) {
} else if (IS_GEN9_LP(dev_priv)) {
else if (IS_GEN9_LP(dev_priv))
else if (IS_GEN9_LP(dev_priv))
if (IS_GEN9_LP(dev_priv))
if (IS_GEN9_LP(dev_priv) && ret)
if (IS_GEN9_LP(dev_priv))
if (IS_GEN9_LP(dev_priv))
} else if (IS_GEN9_LP(dev_priv)) {
sseu->max_slices = IS_GEN9_LP(dev_priv) ? 1 : 3;
sseu->max_subslices = IS_GEN9_LP(dev_priv) ? 3 : 4;
!IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1;
IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1;
if (IS_GEN9_LP(dev_priv)) {
freq = IS_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz;
if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
} else if (IS_GEN9_LP(dev_priv)) {
!IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
!IS_GEN9_LP(dev_priv)) {
else if (IS_GEN9_LP(dev_priv))
if (IS_GEN9_LP(dev_priv) &&
if (IS_GEN9_LP(dev_priv))
if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
} else if (IS_GEN9_LP(dev_priv)) {
else if (IS_GEN9_LP(dev_priv))
if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
(IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
!IS_GEN9_LP(dev_priv)))
if (IS_GEN9_LP(dev_priv))
if (IS_GEN9_LP(dev_priv))
else if (IS_GEN9_LP(dev_priv))
if (IS_GEN9_LP(dev_priv))
if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
else if (IS_GEN9_LP(dev_priv))
else if (IS_GEN9_LP(dev_priv))
if (IS_GEN9_LP(dev_priv))
if (IS_GEN9_LP(dev_priv))
else if (IS_GEN9_LP(dev_priv))
} else if (IS_GEN9_LP(dev_priv)) {
if (IS_GEN9_LP(dev_priv)) {
IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(i915)) {
if (IS_GEN9_LP(dev_priv)) {
if (IS_GEN9_LP(dev_priv)) {
} else if (IS_GEN9_LP(dev_priv)) {
} else if (IS_GEN9_LP(dev_priv)) {
else if (IS_GEN9_LP(dev_priv))
if (IS_GEN9_LP(dev_priv))
if (IS_GEN9_LP(dev_priv))
if (IS_GEN9_LP(i915))
if (IS_GEN9_LP(i915))
if (IS_GEN9_LP(dev_priv))
if (IS_GEN9_LP(dev_priv) && !bxt_dsi_pll_is_enabled(dev_priv))
i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
if (IS_GEN9_LP(dev_priv)) {
if (IS_GEN9_LP(dev_priv)) {
if (IS_GEN9_LP(dev_priv)) {
} else if (IS_GEN9_LP(dev_priv)) {
if (IS_GEN9_LP(dev_priv)) {
if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
if (IS_GEN9_LP(dev_priv))
if (IS_GEN9_LP(dev_priv))
if (IS_GEN9_LP(dev_priv))
if (IS_GEN9_LP(dev_priv)) {
else if (IS_GEN9_LP(dev_priv))
i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
if ((IS_GEN9_LP(dev_priv) || port == PORT_A) &&
if (IS_GEN9_LP(dev_priv)) {
i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
if (IS_GEN9_LP(dev_priv)) {
if (IS_GEN9_LP(dev_priv)) {