sys/dev/drm/i915/i915_drv.c

1615

if (INTEL_INFO(dev_priv)->num_pipes) {

sys/dev/drm/i915/i915_drv.c

1639

if (INTEL_INFO(dev_priv)->num_pipes)

sys/dev/drm/i915/i915_drv.c

1790

if (INTEL_INFO(dev_priv)->num_pipes) {

sys/dev/drm/i915/i915_drv.c

1792

INTEL_INFO(dev_priv)->num_pipes);

sys/dev/drm/i915/i915_drv.c

254

if (INTEL_INFO(dev_priv)->gen < 5)

sys/dev/drm/i915/i915_drv.c

301

if (pch && INTEL_INFO(dev_priv)->num_pipes == 0) {

sys/dev/drm/i915/i915_drv.c

375

value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);

sys/dev/drm/i915/i915_drv.c

380

value = INTEL_INFO(dev_priv)->sseu.eu_total;

sys/dev/drm/i915/i915_drv.c

397

value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;

sys/dev/drm/i915/i915_drv.c

448

value = INTEL_INFO(dev_priv)->sseu.slice_mask;

sys/dev/drm/i915/i915_drv.c

453

value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0];

sys/dev/drm/i915/i915_drv.c

458

value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;

sys/dev/drm/i915/i915_drv.c

461

value = INTEL_INFO(dev_priv)->has_coherent_ggtt;

sys/dev/drm/i915/i915_drv.c

717

if (INTEL_INFO(dev_priv)->num_pipes == 0)

sys/dev/drm/i915/i915_drv.h

2225

for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->ring_mask; \

sys/dev/drm/i915/i915_drv.h

2560

#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)

sys/dev/drm/i915/i915_gem.c

3057

unsigned long supported = INTEL_INFO(i915)->page_sizes;

sys/dev/drm/i915/i915_gem.c

833

if (INTEL_INFO(dev_priv)->has_coherent_ggtt)

sys/dev/drm/i915/i915_gem_execbuffer.c

914

cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;

sys/dev/drm/i915/i915_gem_gtt.c

856

ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->vm.i915)->ring_mask;

sys/dev/drm/i915/i915_gpu_error.c

1765

INTEL_INFO(i915),

sys/dev/drm/i915/i915_irq.c

3297

engine_mask &= INTEL_INFO(dev_priv)->ring_mask;

sys/dev/drm/i915/i915_perf.c

2651

1000ULL * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz);

sys/dev/drm/i915/i915_perf.c

3502

(INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz / 2);

sys/dev/drm/i915/i915_query.c

16

const struct sseu_dev_info *sseu = &INTEL_INFO(dev_priv)->sseu;

sys/dev/drm/i915/intel_bios.c

1724

if (INTEL_INFO(dev_priv)->num_pipes == 0) {

sys/dev/drm/i915/intel_color.c

395

uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;

sys/dev/drm/i915/intel_color.c

425

uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;

sys/dev/drm/i915/intel_color.c

482

INTEL_INFO(dev_priv)->color.degamma_lut_size);

sys/dev/drm/i915/intel_color.c

568

lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;

sys/dev/drm/i915/intel_color.c

583

lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;

sys/dev/drm/i915/intel_color.c

622

degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;

sys/dev/drm/i915/intel_color.c

623

gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;

sys/dev/drm/i915/intel_color.c

669

if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 &&

sys/dev/drm/i915/intel_color.c

670

INTEL_INFO(dev_priv)->color.gamma_lut_size != 0)

sys/dev/drm/i915/intel_color.c

672

INTEL_INFO(dev_priv)->color.degamma_lut_size,

sys/dev/drm/i915/intel_color.c

674

INTEL_INFO(dev_priv)->color.gamma_lut_size);

sys/dev/drm/i915/intel_csr.c

501

WARN_ON(!IS_ALPHA_SUPPORT(INTEL_INFO(dev_priv)));

sys/dev/drm/i915/intel_display.c

13178

INTEL_INFO(dev_priv)->cursor_needs_physical) {

sys/dev/drm/i915/intel_display.c

14286

if (INTEL_INFO(dev_priv)->num_pipes == 0)

sys/dev/drm/i915/intel_display.c

15406

INTEL_INFO(dev_priv)->num_pipes,

sys/dev/drm/i915/intel_display.c

15407

INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");

sys/dev/drm/i915/intel_display.c

16318

if (INTEL_INFO(dev_priv)->num_pipes == 0)

sys/dev/drm/i915/intel_display.c

16359

error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;

sys/dev/drm/i915/intel_display.c

16398

err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);

sys/dev/drm/i915/intel_display.c

5746

val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes);

sys/dev/drm/i915/intel_display.c

6531

if (INTEL_INFO(dev_priv)->num_pipes == 2)

sys/dev/drm/i915/intel_display.c

8691

if (INTEL_INFO(dev_priv)->num_pipes == 3 &&

sys/dev/drm/i915/intel_display.c

9752

if (INTEL_INFO(dev_priv)->cursor_needs_physical)

sys/dev/drm/i915/intel_display.h

106

#define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')

sys/dev/drm/i915/intel_display.h

280

for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)

sys/dev/drm/i915/intel_display.h

283

for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \

sys/dev/drm/i915/intel_display.h

292

(__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \

sys/dev/drm/i915/intel_display.h

297

(__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \

sys/dev/drm/i915/intel_engine_cs.c

329

const unsigned int ring_mask = INTEL_INFO(dev_priv)->ring_mask;

sys/dev/drm/i915/intel_engine_cs.c

767

const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);

sys/dev/drm/i915/intel_fbdev.c

512

num_connectors_enabled < INTEL_INFO(dev_priv)->num_pipes) {

sys/dev/drm/i915/intel_fbdev.c

700

if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0))

sys/dev/drm/i915/intel_guc_submission.c

1076

INTEL_INFO(dev_priv)->ring_mask,

sys/dev/drm/i915/intel_guc_submission.c

1087

INTEL_INFO(dev_priv)->ring_mask,

sys/dev/drm/i915/intel_i2c.c

820

if (INTEL_INFO(dev_priv)->num_pipes == 0)

sys/dev/drm/i915/intel_lpe_audio.c

115

pdata->num_pipes = INTEL_INFO(dev_priv)->num_pipes;

sys/dev/drm/i915/intel_lrc.c

2526

bool subslice_pg = INTEL_INFO(dev_priv)->sseu.has_subslice_pg;

sys/dev/drm/i915/intel_lrc.c

2527

u8 slices = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask);

sys/dev/drm/i915/intel_lrc.c

2528

u8 subslices = hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]);

sys/dev/drm/i915/intel_lrc.c

2576

if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {

sys/dev/drm/i915/intel_lrc.c

2604

if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) {

sys/dev/drm/i915/intel_lrc.c

2607

val = INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<

sys/dev/drm/i915/intel_lrc.c

2614

val = INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<

sys/dev/drm/i915/intel_pm.c

1900

const int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;

sys/dev/drm/i915/intel_pm.c

2642

fifo_size /= INTEL_INFO(dev_priv)->num_pipes;

sys/dev/drm/i915/intel_pm.c

3829

u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;

sys/dev/drm/i915/intel_pm.c

7269

switch (INTEL_INFO(dev_priv)->sseu.eu_total) {

sys/dev/drm/i915/intel_pm.c

7887

if (INTEL_INFO(dev_priv)->is_mobile)

sys/dev/drm/i915/intel_pm.c

9430

if (INTEL_INFO(dev_priv)->num_pipes == 1) {

sys/dev/drm/i915/intel_ringbuffer.c

1565

INTEL_INFO(i915)->num_rings - 1 :

sys/dev/drm/i915/intel_ringbuffer.c

2230

num_rings = INTEL_INFO(dev_priv)->num_rings - 1;

sys/dev/drm/i915/intel_ringbuffer.h

101

1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask[0])

sys/dev/drm/i915/intel_ringbuffer.h

97

1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)

sys/dev/drm/i915/intel_runtime_pm.c

2972

if (IS_GEN9_BC(dev_priv) || INTEL_INFO(dev_priv)->gen >= 10) {

sys/dev/drm/i915/intel_uncore.c

1686

if (INTEL_INFO(dev_priv)->gen_mask & entry->gen_mask &&

sys/dev/drm/i915/intel_workarounds.c

335

if (!is_power_of_2(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]))

sys/dev/drm/i915/intel_workarounds.c

344

ss = ffs(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]) - 1;

sys/dev/drm/i915/intel_workarounds.c

764

const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);