INTEL_GEN
if (INTEL_GEN(dev_priv) < 5)
if (INTEL_GEN(dev_priv) < 9 || IS_GEMINILAKE(dev_priv))
else if (INTEL_GEN(dev_priv) == 9)
if (INTEL_GEN(dev_priv) >= 5) {
if (!(hibernation && INTEL_GEN(dev_priv) < 6))
int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
if (INTEL_GEN(dev_priv) >= 4)
if (INTEL_GEN(dev_priv) >= 4)
int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7)
#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
if (INTEL_GEN(dev_priv) < 6)
else if (INTEL_GEN(dev_priv) >= 5)
if (INTEL_GEN(i915) >= 10)
if (INTEL_GEN(i915) >= 6)
if (INTEL_GEN(i915) >= 6)
if (INTEL_GEN(i915) >= 5)
if (INTEL_GEN(rq->i915) >= 6)
if (INTEL_GEN(i915) >= 5 && intel_has_gpu_reset(i915))
if (INTEL_GEN(dev_priv) < 5 ||
if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
} else if (INTEL_GEN(dev_priv) >= 7) {
if (INTEL_GEN(dev_priv) >= 7 && !IS_VALLEYVIEW(dev_priv) &&
else if (INTEL_GEN(dev_priv) >= 4 ||
if (INTEL_GEN(i915) >= 11)
if (INTEL_GEN(to_i915(dev)) < 4)
cache->gen = INTEL_GEN(i915);
if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) {
} else if (INTEL_GEN(dev_priv) >= 6) {
if (INTEL_GEN(fence->i915) >= 6) {
if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9)
else if (INTEL_GEN(dev_priv) >= 9)
INTEL_GEN(dev_priv) <= 10)
else if (INTEL_GEN(dev_priv) >= 8)
MISSING_CASE(INTEL_GEN(dev_priv));
if (INTEL_GEN(i915) < 8)
if (INTEL_GEN(dev_priv) >= 8)
else if (INTEL_GEN(dev_priv) >= 6)
if (INTEL_GEN(dev_priv) < 6)
if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
if (INTEL_GEN(dev_priv) >= 10)
else if (INTEL_GEN(dev_priv) >= 7)
if (INTEL_GEN(dev_priv) <= 5)
else if (INTEL_GEN(dev_priv) < 8)
if (INTEL_GEN(dev_priv) < 6 && !intel_enable_gtt())
if (INTEL_GEN(dev_priv) >= 8) {
switch (INTEL_GEN(engine->i915)) {
if (INTEL_GEN(dev_priv) <= 4 &&
if (intel_vtd_active() && INTEL_GEN(dev_priv) < 8) {
switch (INTEL_GEN(dev_priv)) {
if (INTEL_GEN(dev_priv) >= 8 && start < 4096)
if (INTEL_GEN(i915) >= 4)
if (INTEL_GEN(i915) >= 7) {
} else if (INTEL_GEN(i915) >= 4) {
if (INTEL_GEN(i915) >= 4) {
if (INTEL_GEN(dev_priv) >= 6) {
} else if (INTEL_GEN(dev_priv) >= 4) {
if (INTEL_GEN(dev_priv) >= 6) {
if (INTEL_GEN(dev_priv) >= 8) {
if (INTEL_GEN(dev_priv) >= 4) {
if (INTEL_GEN(dev_priv) >= 8) {
if (INTEL_GEN(dev_priv) > 2)
else if (INTEL_GEN(dev_priv) >= 8)
if (INTEL_GEN(dev_priv) >= 8) {
if (INTEL_GEN(dev_priv) >= 7)
if (INTEL_GEN(dev_priv) >= 6) {
if (INTEL_GEN(dev_priv) >= 5)
if (INTEL_GEN(dev_priv) >= 11) {
} else if (INTEL_GEN(dev_priv) >= 8) {
INTEL_GEN(dev_priv), engine_id, ecode);
if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3)
if (INTEL_GEN(m->i915) <= 6)
if (INTEL_GEN(m->i915) >= 4) {
if (INTEL_GEN(m->i915) >= 6) {
if (INTEL_GEN(m->i915) >= 8) {
if (INTEL_GEN(dev_priv) >= 6) {
if (INTEL_GEN(dev_priv) >= 8)
if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
(INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
if (INTEL_GEN(dev_priv) >= 3)
if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
if (INTEL_GEN(dev_priv) >= 8)
if (INTEL_GEN(dev_priv) >= 6)
if (INTEL_GEN(dev_priv) >= 7)
if (INTEL_GEN(dev_priv) >= 6) {
if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
if (INTEL_GEN(dev_priv) >= 9)
if (INTEL_GEN(dev_priv) >= 11)
INTEL_GEN(dev_priv) >= 11)
if (INTEL_GEN(dev_priv) >= 9)
if (INTEL_GEN(dev_priv) < 4)
if (INTEL_GEN(dev_priv) >= 8) {
} else if (INTEL_GEN(dev_priv) >= 6) {
uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
if (INTEL_GEN(dev_priv) >= 6)
WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11);
return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
if (INTEL_GEN(dev_priv) >= 11)
else if (INTEL_GEN(dev_priv) >= 8)
if (INTEL_GEN(dev_priv) >= 11)
else if (INTEL_GEN(dev_priv) >= 8)
if (INTEL_GEN(dev_priv) >= 8) {
} else if (INTEL_GEN(dev_priv) >= 7) {
if (INTEL_GEN(dev_priv) >= 6) {
if (INTEL_GEN(dev_priv) >= 7) {
if (INTEL_GEN(dev_priv) <= 10)
if (INTEL_GEN(dev_priv) >= 9) {
if (INTEL_GEN(dev_priv) >= 11)
if (IS_CNL_WITH_PORT_F(dev_priv) || INTEL_GEN(dev_priv) >= 11)
if (INTEL_GEN(dev_priv) >= 11) {
if (INTEL_GEN(dev_priv) <= 7)
if (INTEL_GEN(dev_priv) >= 8)
} else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
} else if (INTEL_GEN(dev_priv) >= 11) {
} else if (INTEL_GEN(dev_priv) >= 8) {
if (INTEL_GEN(dev_priv) >= 11)
if (INTEL_GEN(dev_priv) >= 11)
if (INTEL_GEN(dev_priv) < 5)
if (INTEL_GEN(dev_priv) >= 4)
switch (INTEL_GEN(i915)) {
MISSING_CASE(INTEL_GEN(i915));
if (INTEL_GEN(dev_priv) < 8) {
if (INTEL_GEN(i915) <= 2) {
if (INTEL_GEN(engine->i915) < 6)
if (INTEL_GEN(i915) < 6)
#define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \
#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \
if (INTEL_GEN(dev_priv) < 7)
if (INTEL_GEN(dev_priv) <= 4)
if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
if (INTEL_GEN(dev_priv) <= 4)
if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
if (INTEL_GEN(dev_priv) < 7)
else if (INTEL_GEN(dev_priv) >= 6)
if ((INTEL_GEN(dev_priv) >= 9) &&
if (INTEL_GEN(dev_priv) == 9 &&
} else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) {
switch (INTEL_GEN(dev_priv)) {
if (INTEL_GEN(dev_priv) >= 5) {
INTEL_GEN(dev_priv) >= 10)) {
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
if (INTEL_GEN(dev_priv) >= 9)
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
else if (INTEL_GEN(dev_priv) < 4)
if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
if (INTEL_GEN(dev_priv) > 6) {
if (INTEL_GEN(dev_priv) >= 5)
else if (INTEL_GEN(dev_priv) < 4)
if (INTEL_GEN(dev_priv) >= 5) {
if (INTEL_GEN(dev_priv) >= 11)
if (INTEL_GEN(dev_priv) >= 11) {
if (INTEL_GEN(dev_priv) <= 8)
} else if (INTEL_GEN(dev_priv) < 9) {
} else if (INTEL_GEN(dev_priv) < 9) {
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
if (INTEL_GEN(dev_priv) >= 11)
if (INTEL_GEN(dev_priv) >= 11)
if (INTEL_GEN(dev_priv) <= 4) {
} else if (INTEL_GEN(dev_priv) <= 8) {
} else if (INTEL_GEN(dev_priv) <= 9) {
} else if (INTEL_GEN(dev_priv) <= 11) {
if (INTEL_GEN(dev_priv) <= 10)
if (INTEL_GEN(dev_priv) >= 10) {
} else if (INTEL_GEN(dev_priv) == 9) {
} else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
else if (INTEL_GEN(dev_priv) == 9)
else if (INTEL_GEN(dev_priv) == 10)
else if (INTEL_GEN(dev_priv) >= 11)
if (INTEL_GEN(dev_priv) < 11)
if (INTEL_GEN(dev_priv) <= 10) {
if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
if (INTEL_GEN(dev_priv) >= 4) {
if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
if (INTEL_GEN(dev_priv) >= 9) {
else if (INTEL_GEN(dev_priv) >= 5)
if (INTEL_GEN(dev_priv) >= 9)
if (INTEL_GEN(dev_priv) >= 9)
if (INTEL_GEN(dev_priv) < 8) {
if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
if (INTEL_GEN(dev_priv) < 4)
if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
if (INTEL_GEN(dev_priv) >= 11)
if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
if (INTEL_GEN(to_i915(crtc->dev)) < 6)
if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
else if (INTEL_GEN(dev_priv) >= 9)
else if (INTEL_GEN(dev_priv) >= 4)
if (INTEL_GEN(dev_priv) >= 11)
if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
if (INTEL_GEN(dev_priv) >= 9)
if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
if (INTEL_GEN(dev_priv) >= 9)
if (INTEL_GEN(dev_priv) >= 9) {
} else if (INTEL_GEN(dev_priv) >= 4) {
if (INTEL_GEN(dev_priv) >= 9)
else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
if (INTEL_GEN(dev_priv) >= 10) {
} else if (INTEL_GEN(dev_priv) >= 9) {
} else if (INTEL_GEN(dev_priv) >= 4) {
if (INTEL_GEN(dev_priv) >= 4)
if (INTEL_GEN(dev_priv) >= 9)
if (INTEL_GEN(dev_priv) >= 4)
if (INTEL_GEN(dev_priv) >= 9)
if (INTEL_GEN(dev_priv) < 9) {
if (INTEL_GEN(dev_priv) >= 9)
if (INTEL_GEN(dev_priv) < 9) {
if (INTEL_GEN(dev_priv) < 4 &&
if (INTEL_GEN(dev_priv) > 3) {
INTEL_GEN(dev_priv) < 9) {
if (INTEL_GEN(dev_priv) < 4) {
if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
if (INTEL_GEN(dev_priv) < 9 || IS_SKYLAKE(dev_priv) ||
IS_BROXTON(dev_priv) || INTEL_GEN(dev_priv) >= 11) {
if (INTEL_GEN(dev_priv) >= 9 ||
} else if (INTEL_GEN(dev_priv) >= 3) {
if (INTEL_GEN(dev_priv) >= 9) {
if (INTEL_GEN(dev_priv) >= 9)
if (INTEL_GEN(dev_priv) >= 4) {
if (INTEL_GEN(dev_priv) >= 4)
} else if (INTEL_GEN(dev_priv) >= 9) {
unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
if (INTEL_GEN(dev_priv) <= 3) {
if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
if (INTEL_GEN(dev_priv) >= 4) {
if (INTEL_GEN(dev_priv) <= 3) {
if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
if (INTEL_GEN(dev_priv) >= 4) {
if (INTEL_GEN(dev_priv) >= 9)
else if (INTEL_GEN(dev_priv) >= 4)
if (INTEL_GEN(dev_priv) >= 9)
return INTEL_GEN(dev_priv) < 4 || plane->has_fbc;
if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
} else if (INTEL_GEN(dev_priv) >= 4) {
} else if (INTEL_GEN(dev_priv) >= 3) {
if (INTEL_GEN(dev_priv) < 5)
if (INTEL_GEN(dev_priv) >= 4 &&
if (INTEL_GEN(dev_priv) >= 4)
if (INTEL_GEN(dev_priv) >= 4)
if (INTEL_GEN(dev_priv) < 4) {
} else if (INTEL_GEN(dev_priv) >= 4) {
if (INTEL_GEN(dev_priv) >= 4)
if (INTEL_GEN(dev_priv) >= 5)
if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
if (INTEL_GEN(dev_priv) >= 10)
if (INTEL_GEN(dev_priv) < 11) {
INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
if (INTEL_GEN(dev_priv) >= 9) {
if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
if (INTEL_GEN(dev_priv) >= 11)
if (INTEL_GEN(dev_priv) >= 9)
if (INTEL_GEN(dev_priv) >= 11) {
if (INTEL_GEN(dev_priv) >= 11)
if (INTEL_GEN(dev_priv) >= 9)
if (INTEL_GEN(dev_priv) >= 11)
return INTEL_GEN(dev_priv) < 4 &&
if (INTEL_GEN(dev_priv) < 4) {
if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
if (INTEL_GEN(dev_priv) >= 5) {
INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
if (INTEL_GEN(dev_priv) >= 4)
if (INTEL_GEN(dev_priv) >= 4) {
if (INTEL_GEN(dev_priv) > 3)
if (INTEL_GEN(dev_priv) < 4 ||
if (INTEL_GEN(dev_priv) <= 3 &&
if (INTEL_GEN(dev_priv) < 4) {
if (INTEL_GEN(dev_priv) >= 4) {
} else if (INTEL_GEN(dev_priv) >= 4) {
if (INTEL_GEN(dev_priv) < 4)
if (INTEL_GEN(dev_priv) >= 4) {
if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
if (INTEL_GEN(dev_priv) >= 5) {
if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
if (INTEL_GEN(dev_priv) >= 11)
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
if (INTEL_GEN(dev_priv) >= 10 &&
if (INTEL_GEN(dev_priv) < 9 &&
if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
if (INTEL_GEN(dev_priv) >= 9)
if (INTEL_GEN(dev_priv) >= 9) {
if (INTEL_GEN(dev_priv) >= 9)
if (INTEL_GEN(dev_priv) >= 9)
if (INTEL_GEN(dev_priv) >= 9) {
if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
if (INTEL_GEN(dev_priv) >= 10) {
if (INTEL_GEN(dev_priv) == 10)
if (INTEL_GEN(dev_priv) < 5)
if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
} else if (INTEL_GEN(dev_priv) > 6) {
if (INTEL_GEN(dev_priv) <= 6) {
if (INTEL_GEN(dev_priv) < 9) {
if (INTEL_GEN(dev_priv) < 5)
if (INTEL_GEN(dev_priv) >= 11 && ref_clock == 38400)
switch (INTEL_GEN(engine->i915)) {
if (INTEL_GEN(engine->i915) > 2) {
if (INTEL_GEN(dev_priv) >= 6) {
if (INTEL_GEN(dev_priv) >= 8)
else if (INTEL_GEN(dev_priv) >= 4)
if (INTEL_GEN(dev_priv) >= 4) {
} else if (INTEL_GEN(dev_priv) > 6) {
switch (INTEL_GEN(dev_priv)) {
MISSING_CASE(INTEL_GEN(dev_priv));
if (INTEL_GEN(dev_priv) < 8)
if (INTEL_GEN(i915) >= bases[i].gen)
if (INTEL_GEN(dev_priv) >= 8)
else if (INTEL_GEN(dev_priv) >= 4)
if (INTEL_GEN(dev_priv) >= 8)
if (INTEL_GEN(dev_priv) < 3)
if (INTEL_GEN(dev_priv) == 10)
else if (INTEL_GEN(dev_priv) >= 11)
if (INTEL_GEN(dev_priv) >= 11) {
switch (INTEL_GEN(dev_priv)) {
if (INTEL_GEN(dev_priv) > 2 && !(I915_READ_MODE(engine) & MODE_IDLE))
if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv))
if (INTEL_GEN(dev_priv) >= 5)
if (INTEL_GEN(dev_priv) >= 7)
else if (INTEL_GEN(dev_priv) >= 5)
if (INTEL_GEN(dev_priv) >= 5)
if (ret && INTEL_GEN(dev_priv) <= 4) {
return INTEL_GEN(dev_priv) <= 3;
if (INTEL_GEN(dev_priv) >= 5)
if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
} else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
if (INTEL_GEN(dev_priv) == 7)
else if (INTEL_GEN(dev_priv) >= 8)
else if (INTEL_GEN(dev_priv) >= 8)
backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4;
return ((INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) &&
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
else if (INTEL_GEN(dev_priv) >= 5)
if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
return INTEL_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
switch (INTEL_GEN(engine->i915)) {
MISSING_CASE(INTEL_GEN(engine->i915));
if (INTEL_GEN(dev_priv) >= 11)
if (INTEL_GEN(engine->i915) < 11) {
if (INTEL_GEN(engine->i915) < 11) {
if (INTEL_GEN(ctx->i915) >= 11) {
if (INTEL_GEN(dev_priv) >= 9)
if (INTEL_GEN(dev_priv) < 9)
if (INTEL_GEN(dev_priv) >= 11) {
switch (INTEL_GEN(engine->i915)) {
MISSING_CASE(INTEL_GEN(engine->i915));
if (INTEL_GEN(dev_priv) < 11) {
if (INTEL_GEN(dev_priv) >= 10)
if (ctx == ctx->i915->preempt_context && INTEL_GEN(engine->i915) < 11)
if (INTEL_GEN(dev_priv) < 5)
if (INTEL_GEN(dev_priv) < 4) {
if (INTEL_GEN(dev_priv) <= 4 &&
if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
if (INTEL_GEN(dev_priv) <= 4 &&
WARN_ONCE(INTEL_GEN(dev_priv) >= 9,
if (INTEL_GEN(dev_priv) >= 4) {
if (INTEL_GEN(dev_priv) >= 4)
if (INTEL_GEN(dev_priv) >= 4)
if (INTEL_GEN(dev_priv) >= 4)
if (INTEL_GEN(dev_priv) < 4 && pipe_config->pipe_bpp == 18)
if (INTEL_GEN(dev_priv) < 4)
if (INTEL_GEN(dev_priv) >= 8)
else if (INTEL_GEN(dev_priv) >= 7)
if (INTEL_GEN(dev_priv) >= 8)
else if (INTEL_GEN(dev_priv) >= 7)
if (INTEL_GEN(dev_priv) >= 7)
if (INTEL_GEN(dev_priv) >= 8)
if (INTEL_GEN(dev_priv) <= 6)
if (INTEL_GEN(dev_priv) >= 9) {
} else if (INTEL_GEN(dev_priv) >= 6) {
} else if (INTEL_GEN(dev_priv) >= 5) {
if (INTEL_GEN(dev_priv) >= 9)
else if (INTEL_GEN(dev_priv) >= 6)
if (INTEL_GEN(dev_priv) >= 9)
if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
if (INTEL_GEN(dev_priv) >= 8)
if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
if (INTEL_GEN(dev_priv) >= 7) {
if (INTEL_GEN(dev_priv) < 11)
if (INTEL_GEN(dev_priv) < 11)
if (INTEL_GEN(dev_priv) >= 11)
if (INTEL_GEN(dev_priv) < 11)
if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
if (INTEL_GEN(dev_priv) >= 10)
if (INTEL_GEN(dev_priv) >= 11 &&
if (INTEL_GEN(dev_priv) >= 10)
if (INTEL_GEN(dev_priv) >= 11) {
if (INTEL_GEN(dev_priv) <= 9)
if (INTEL_GEN(dev_priv) >= 10)
if (INTEL_GEN(dev_priv) >= 11)
if (INTEL_GEN(dev_priv) >= 7 &&
if (INTEL_GEN(dev_priv) >= 7) {
if (INTEL_GEN(dev_priv) >= 9) {
if (INTEL_GEN(i915) < 6)
if (INTEL_GEN(dev_priv) >= 9)
IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
if (INTEL_GEN(dev_priv) >= 10) {
if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
} else if (INTEL_GEN(dev_priv) >= 8) {
else if (INTEL_GEN(dev_priv) >= 6)
if (INTEL_GEN(dev_priv) < 6)
if (INTEL_GEN(dev_priv) >= 11)
else if (INTEL_GEN(dev_priv) >= 6)
if (INTEL_GEN(dev_priv) >= 9)
else if (INTEL_GEN(dev_priv) >= 6)
if (INTEL_GEN(dev_priv) >= 9)
else if (INTEL_GEN(dev_priv) >= 6)
else if (INTEL_GEN(dev_priv) >= 9)
else if (INTEL_GEN(dev_priv) >= 6)
} else if (INTEL_GEN(dev_priv) >= 9) {
} else if (INTEL_GEN(dev_priv) >= 6) {
if (INTEL_GEN(dev_priv) >= 9) {
if (INTEL_GEN(dev_priv) > 6)
if (INTEL_GEN(dev_priv) > 6)
if (INTEL_GEN(dev_priv) >= 9)
if (INTEL_GEN(dev_priv) >= 9)
if (INTEL_GEN(dev_priv) >= 9)
if (INTEL_GEN(dev_priv) >= 8)
if (INTEL_GEN(dev_priv) >= 9) {
if (INTEL_GEN(dev_priv) >= 9 &&
if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8)
if (INTEL_GEN(dev_priv) >= 8)
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
if (INTEL_GEN(dev_priv) >= 9)
if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv))
if (INTEL_GEN(dev_priv) >= 8) {
WARN_ON(INTEL_GEN(dev_priv) > 2 &&
GEM_BUG_ON(INTEL_GEN(dev_priv) < 6);
if (INTEL_GEN(dev_priv) >= 6) {
} else if (INTEL_GEN(dev_priv) >= 5) {
} else if (INTEL_GEN(dev_priv) >= 3) {
GEM_BUG_ON(INTEL_GEN(dev_priv) >= 8);
if (INTEL_GEN(dev_priv) >= 6)
else if (INTEL_GEN(dev_priv) >= 4)
if (INTEL_GEN(dev_priv) >= 6) {
if (INTEL_GEN(dev_priv) < 4)
if (INTEL_GEN(dev_priv) >= 6) {
if (INTEL_GEN(dev_priv) >= 4)
if (INTEL_GEN(dev_priv) >= 6) {
if (INTEL_GEN(dev_priv) > 2) {
if (INTEL_GEN(dev_priv) > 2)
if (INTEL_GEN(dev_priv) >= 6)
(INTEL_GEN(dev_priv__) == 7 ? \
(INTEL_GEN(dev_priv__) == 7 ? \
if (INTEL_GEN(dev_priv) < 11)
pg = INTEL_GEN(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
if (INTEL_GEN(dev_priv) >= 4) {
if (INTEL_GEN(dev_priv) < 5)
WARN_ON_ONCE(INTEL_GEN(dev_priv) < 4);
if (INTEL_GEN(dev_priv) >= 4) {
INTEL_GEN(dev_priv) < 5)
if (INTEL_GEN(dev_priv) >= 4 && IS_MOBILE(dev_priv)) {
if (INTEL_GEN(dev_priv) >= 4 &&
if (INTEL_GEN(dev_priv) < 7) {
if (INTEL_GEN(dev_priv) >= 7)
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
return INTEL_GEN(dev_priv) >= 9;
if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_PRIMARY &&
if (INTEL_GEN(dev_priv) >= 9 &&
if (INTEL_GEN(dev_priv) >= 10)
if (INTEL_GEN(dev_priv) >= 9) {
} else if (INTEL_GEN(dev_priv) >= 7) {
if (INTEL_GEN(dev_priv) >= 9) {
if (INTEL_GEN(dev_priv) >= 9)
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
if (INTEL_GEN(dev_priv) >= 4)
} else if (INTEL_GEN(i915) < 11) {
if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv))
if (INTEL_GEN(dev_priv) >= 11) {
if (INTEL_GEN(dev_priv) >= 11) {
if (INTEL_GEN(dev_priv) < 3)
if (INTEL_GEN(i915) >= 11)
if (INTEL_GEN(dev_priv) >= 8)
else if (INTEL_GEN(dev_priv) >= 6)
else if (INTEL_GEN(dev_priv) >= 3)
u32 guc_domain = INTEL_GEN(dev_priv) >= 11 ? GEN11_GRDOM_GUC :
if (INTEL_GEN(dev_priv) >= 11) {
} else if (INTEL_GEN(dev_priv) >= 6) {
if (INTEL_GEN(dev_priv) >= 11) {
if (INTEL_GEN(dev_priv) < 9)
INTEL_GEN(dev_priv) >= 9) {
(INTEL_GEN(dev_priv) >= 9 || \
else if (INTEL_GEN(i915) >= 10)
if (INTEL_GEN(i915) < 8)
MISSING_CASE(INTEL_GEN(i915));
if (GEM_WARN_ON(INTEL_GEN(engine->i915) < 8))
if (INTEL_GEN(dev_priv) < 8)
MISSING_CASE(INTEL_GEN(dev_priv));
if (INTEL_GEN(dev_priv) >= 10 &&
if (INTEL_GEN(dev_priv) >= 11)
if (INTEL_GEN(i915) < 8)
MISSING_CASE(INTEL_GEN(i915));