sys/dev/drm/amd/amdgpu/cz_ih.c

128

ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);

sys/dev/drm/amd/amdgpu/cz_ih.c

129

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

sys/dev/drm/amd/amdgpu/cz_ih.c

130

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

sys/dev/drm/amd/amdgpu/cz_ih.c

133

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);

sys/dev/drm/amd/amdgpu/cz_ih.c

204

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

sys/dev/drm/amd/amdgpu/cz_ih.c

64

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);

sys/dev/drm/amd/amdgpu/cz_ih.c

82

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);

sys/dev/drm/amd/amdgpu/iceland_ih.c

128

ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);

sys/dev/drm/amd/amdgpu/iceland_ih.c

129

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

sys/dev/drm/amd/amdgpu/iceland_ih.c

130

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

sys/dev/drm/amd/amdgpu/iceland_ih.c

133

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);

sys/dev/drm/amd/amdgpu/iceland_ih.c

204

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

sys/dev/drm/amd/amdgpu/iceland_ih.c

64

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);

sys/dev/drm/amd/amdgpu/iceland_ih.c

82

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);

sys/dev/drm/amd/amdgpu/tonga_ih.c

127

ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

sys/dev/drm/amd/amdgpu/tonga_ih.c

128

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

sys/dev/drm/amd/amdgpu/tonga_ih.c

130

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);

sys/dev/drm/amd/amdgpu/tonga_ih.c

131

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);

sys/dev/drm/amd/amdgpu/tonga_ih.c

134

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1);

sys/dev/drm/amd/amdgpu/tonga_ih.c

215

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

sys/dev/drm/amd/amdgpu/tonga_ih.c

62

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);

sys/dev/drm/amd/amdgpu/tonga_ih.c

63

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);

sys/dev/drm/amd/amdgpu/tonga_ih.c

79

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);

sys/dev/drm/amd/amdgpu/tonga_ih.c

80

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);

sys/dev/drm/amd/amdgpu/vega10_ih.c

105

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 1);

sys/dev/drm/amd/amdgpu/vega10_ih.c

109

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 4);

sys/dev/drm/amd/amdgpu/vega10_ih.c

112

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

sys/dev/drm/amd/amdgpu/vega10_ih.c

113

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);

sys/dev/drm/amd/amdgpu/vega10_ih.c

114

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

sys/dev/drm/amd/amdgpu/vega10_ih.c

116

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);

sys/dev/drm/amd/amdgpu/vega10_ih.c

117

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);

sys/dev/drm/amd/amdgpu/vega10_ih.c

118

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);

sys/dev/drm/amd/amdgpu/vega10_ih.c

119

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);

sys/dev/drm/amd/amdgpu/vega10_ih.c

122

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1);

sys/dev/drm/amd/amdgpu/vega10_ih.c

216

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

sys/dev/drm/amd/amdgpu/vega10_ih.c

49

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);

sys/dev/drm/amd/amdgpu/vega10_ih.c

50

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);

sys/dev/drm/amd/amdgpu/vega10_ih.c

66

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);

sys/dev/drm/amd/amdgpu/vega10_ih.c

67

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);

sys/dev/drm/radeon/cik.c

6842

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

sys/dev/drm/radeon/cik.c

6847

WREG32(IH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/radeon/cik.c

6860

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

sys/dev/drm/radeon/cik.c

6865

WREG32(IH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/radeon/cik.c

7009

WREG32(IH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/radeon/cik.c

7526

tmp = RREG32(IH_RB_CNTL);

sys/dev/drm/radeon/cik.c

7528

WREG32(IH_RB_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

4676

tmp = RREG32(IH_RB_CNTL);

sys/dev/drm/radeon/evergreen.c

4678

WREG32(IH_RB_CNTL, tmp);

sys/dev/drm/radeon/r600.c

3607

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

sys/dev/drm/radeon/r600.c

3612

WREG32(IH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/radeon/r600.c

3618

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

sys/dev/drm/radeon/r600.c

3623

WREG32(IH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/radeon/r600.c

3735

WREG32(IH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/radeon/r600.c

4069

tmp = RREG32(IH_RB_CNTL);

sys/dev/drm/radeon/r600.c

4071

WREG32(IH_RB_CNTL, tmp);

sys/dev/drm/radeon/si.c

5909

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

sys/dev/drm/radeon/si.c

5914

WREG32(IH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/radeon/si.c

5920

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

sys/dev/drm/radeon/si.c

5925

WREG32(IH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/radeon/si.c

6011

WREG32(IH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/radeon/si.c

6214

tmp = RREG32(IH_RB_CNTL);

sys/dev/drm/radeon/si.c

6216

WREG32(IH_RB_CNTL, tmp);