sys/dev/drm/amd/amdgpu/cz_ih.c

148

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0);

sys/dev/drm/amd/amdgpu/cz_ih.c

151

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1);

sys/dev/drm/amd/amdgpu/cz_ih.c

63

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);

sys/dev/drm/amd/amdgpu/cz_ih.c

83

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);

sys/dev/drm/amd/amdgpu/iceland_ih.c

148

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0);

sys/dev/drm/amd/amdgpu/iceland_ih.c

151

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1);

sys/dev/drm/amd/amdgpu/iceland_ih.c

63

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);

sys/dev/drm/amd/amdgpu/iceland_ih.c

83

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);

sys/dev/drm/radeon/cik.c

6841

u32 ih_cntl = RREG32(IH_CNTL);

sys/dev/drm/radeon/cik.c

6846

WREG32(IH_CNTL, ih_cntl);

sys/dev/drm/radeon/cik.c

6861

u32 ih_cntl = RREG32(IH_CNTL);

sys/dev/drm/radeon/cik.c

6866

WREG32(IH_CNTL, ih_cntl);

sys/dev/drm/radeon/cik.c

7020

WREG32(IH_CNTL, ih_cntl);

sys/dev/drm/radeon/r600.c

3606

u32 ih_cntl = RREG32(IH_CNTL);

sys/dev/drm/radeon/r600.c

3611

WREG32(IH_CNTL, ih_cntl);

sys/dev/drm/radeon/r600.c

3619

u32 ih_cntl = RREG32(IH_CNTL);

sys/dev/drm/radeon/r600.c

3624

WREG32(IH_CNTL, ih_cntl);

sys/dev/drm/radeon/r600.c

3746

WREG32(IH_CNTL, ih_cntl);

sys/dev/drm/radeon/si.c

5908

u32 ih_cntl = RREG32(IH_CNTL);

sys/dev/drm/radeon/si.c

5913

WREG32(IH_CNTL, ih_cntl);

sys/dev/drm/radeon/si.c

5921

u32 ih_cntl = RREG32(IH_CNTL);

sys/dev/drm/radeon/si.c

5926

WREG32(IH_CNTL, ih_cntl);

sys/dev/drm/radeon/si.c

6022

WREG32(IH_CNTL, ih_cntl);