sys/dev/drm/i915/i915_drv.h

3704

#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)

sys/dev/drm/i915/i915_gpu_error.c

1656

error->forcewake = I915_READ_FW(FORCEWAKE_VLV);

sys/dev/drm/i915/i915_gpu_error.c

1668

error->forcewake = I915_READ_FW(FORCEWAKE);

sys/dev/drm/i915/i915_gpu_error.c

1675

error->forcewake = I915_READ_FW(FORCEWAKE_MT);

sys/dev/drm/i915/i915_irq.c

1043

position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;

sys/dev/drm/i915/i915_irq.c

2901

master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);

sys/dev/drm/i915/i915_irq.c

853

high1 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;

sys/dev/drm/i915/i915_irq.c

854

low = I915_READ_FW(low_frame);

sys/dev/drm/i915/i915_irq.c

855

high2 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;

sys/dev/drm/i915/i915_irq.c

911

scan_prev_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));

sys/dev/drm/i915/i915_irq.c

917

scan_curr_time = I915_READ_FW(IVB_TIMESTAMP_CTR);

sys/dev/drm/i915/i915_irq.c

919

scan_post_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));

sys/dev/drm/i915/i915_irq.c

954

position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;

sys/dev/drm/i915/i915_irq.c

956

position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;

sys/dev/drm/i915/i915_irq.c

975

temp = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;

sys/dev/drm/i915/i915_pmu.c

196

val = I915_READ_FW(RING_CTL(engine->mmio_base));

sys/dev/drm/i915/intel_engine_cs.c

818

mcr = I915_READ_FW(GEN8_MCR_SELECTOR);

sys/dev/drm/i915/intel_engine_cs.c

827

ret = I915_READ_FW(reg);

sys/dev/drm/i915/intel_i2c.c

324

ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2);

sys/dev/drm/i915/intel_i2c.c

326

ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50);

sys/dev/drm/i915/intel_i2c.c

405

val = I915_READ_FW(GMBUS3);

sys/dev/drm/i915/intel_pm.c

1972

dsparb = I915_READ_FW(DSPARB);

sys/dev/drm/i915/intel_pm.c

1973

dsparb2 = I915_READ_FW(DSPARB2);

sys/dev/drm/i915/intel_pm.c

1989

dsparb = I915_READ_FW(DSPARB);

sys/dev/drm/i915/intel_pm.c

1990

dsparb2 = I915_READ_FW(DSPARB2);

sys/dev/drm/i915/intel_pm.c

2006

dsparb3 = I915_READ_FW(DSPARB3);

sys/dev/drm/i915/intel_pm.c

2007

dsparb2 = I915_READ_FW(DSPARB2);

sys/dev/drm/i915/intel_pm.c

9445

I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;

sys/dev/drm/i915/intel_pm.c

9468

I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;

sys/dev/drm/i915/intel_pm.c

9498

if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {

sys/dev/drm/i915/intel_pm.c

9516

*val = I915_READ_FW(GEN6_PCODE_DATA);

sys/dev/drm/i915/intel_pm.c

9546

if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {

sys/dev/drm/i915/intel_pm.c

9755

upper = I915_READ_FW(reg);

sys/dev/drm/i915/intel_pm.c

9761

lower = I915_READ_FW(reg);

sys/dev/drm/i915/intel_pm.c

9765

upper = I915_READ_FW(reg);

sys/dev/drm/i915/intel_pm.c

9823

time_hw = I915_READ_FW(reg);

sys/dev/drm/i915/intel_uncore.c

1725

I915_WRITE_FW(RING_HEAD(base), I915_READ_FW(RING_TAIL(base)));

sys/dev/drm/i915/intel_uncore.c

1736

if (I915_READ_FW(RING_HEAD(base)) != 0)

sys/dev/drm/i915/intel_uncore.c

2013

#define done (((reg_value = I915_READ_FW(reg)) & mask) == value)

sys/dev/drm/i915/intel_workarounds.c

966

u32 val = I915_READ_FW(wa->reg);