sys/dev/drm/i915/i915_drv.c
1223
val_ch0 = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
sys/dev/drm/i915/i915_drv.c
1228
val_ch1 = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
sys/dev/drm/i915/i915_drv.c
1276
val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
sys/dev/drm/i915/i915_drv.c
1301
val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);
sys/dev/drm/i915/i915_drv.c
1324
val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
sys/dev/drm/i915/i915_drv.c
2649
s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
sys/dev/drm/i915/i915_drv.c
2650
s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
sys/dev/drm/i915/i915_drv.c
2651
s->arb_mode = I915_READ(ARB_MODE);
sys/dev/drm/i915/i915_drv.c
2652
s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
sys/dev/drm/i915/i915_drv.c
2653
s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
sys/dev/drm/i915/i915_drv.c
2656
s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
sys/dev/drm/i915/i915_drv.c
2658
s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
sys/dev/drm/i915/i915_drv.c
2659
s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
sys/dev/drm/i915/i915_drv.c
2661
s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
sys/dev/drm/i915/i915_drv.c
2662
s->ecochk = I915_READ(GAM_ECOCHK);
sys/dev/drm/i915/i915_drv.c
2663
s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
sys/dev/drm/i915/i915_drv.c
2664
s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
sys/dev/drm/i915/i915_drv.c
2666
s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
sys/dev/drm/i915/i915_drv.c
2669
s->g3dctl = I915_READ(VLV_G3DCTL);
sys/dev/drm/i915/i915_drv.c
2670
s->gsckgctl = I915_READ(VLV_GSCKGCTL);
sys/dev/drm/i915/i915_drv.c
2671
s->mbctl = I915_READ(GEN6_MBCTL);
sys/dev/drm/i915/i915_drv.c
2674
s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
sys/dev/drm/i915/i915_drv.c
2675
s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
sys/dev/drm/i915/i915_drv.c
2676
s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
sys/dev/drm/i915/i915_drv.c
2677
s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
sys/dev/drm/i915/i915_drv.c
2678
s->rstctl = I915_READ(GEN6_RSTCTL);
sys/dev/drm/i915/i915_drv.c
2679
s->misccpctl = I915_READ(GEN7_MISCCPCTL);
sys/dev/drm/i915/i915_drv.c
2682
s->gfxpause = I915_READ(GEN6_GFXPAUSE);
sys/dev/drm/i915/i915_drv.c
2683
s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
sys/dev/drm/i915/i915_drv.c
2684
s->rpdeuc = I915_READ(GEN6_RPDEUC);
sys/dev/drm/i915/i915_drv.c
2685
s->ecobus = I915_READ(ECOBUS);
sys/dev/drm/i915/i915_drv.c
2686
s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
sys/dev/drm/i915/i915_drv.c
2687
s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
sys/dev/drm/i915/i915_drv.c
2688
s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
sys/dev/drm/i915/i915_drv.c
2689
s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
sys/dev/drm/i915/i915_drv.c
2690
s->rcedata = I915_READ(VLV_RCEDATA);
sys/dev/drm/i915/i915_drv.c
2691
s->spare2gh = I915_READ(VLV_SPAREG2H);
sys/dev/drm/i915/i915_drv.c
2694
s->gt_imr = I915_READ(GTIMR);
sys/dev/drm/i915/i915_drv.c
2695
s->gt_ier = I915_READ(GTIER);
sys/dev/drm/i915/i915_drv.c
2696
s->pm_imr = I915_READ(GEN6_PMIMR);
sys/dev/drm/i915/i915_drv.c
2697
s->pm_ier = I915_READ(GEN6_PMIER);
sys/dev/drm/i915/i915_drv.c
2700
s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
sys/dev/drm/i915/i915_drv.c
2703
s->tilectl = I915_READ(TILECTL);
sys/dev/drm/i915/i915_drv.c
2704
s->gt_fifoctl = I915_READ(GTFIFOCTL);
sys/dev/drm/i915/i915_drv.c
2705
s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
sys/dev/drm/i915/i915_drv.c
2706
s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
sys/dev/drm/i915/i915_drv.c
2707
s->pmwgicz = I915_READ(VLV_PMWGICZ);
sys/dev/drm/i915/i915_drv.c
2710
s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
sys/dev/drm/i915/i915_drv.c
2711
s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
sys/dev/drm/i915/i915_drv.c
2712
s->pcbr = I915_READ(VLV_PCBR);
sys/dev/drm/i915/i915_drv.c
2713
s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
sys/dev/drm/i915/i915_drv.c
2792
val = I915_READ(VLV_GTLC_WAKE_CTRL);
sys/dev/drm/i915/i915_drv.c
2797
val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
sys/dev/drm/i915/i915_drv.c
2831
val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
sys/dev/drm/i915/i915_drv.c
2847
I915_READ(VLV_GTLC_SURVIVABILITY_REG));
sys/dev/drm/i915/i915_drv.c
2859
val = I915_READ(VLV_GTLC_WAKE_CTRL);
sys/dev/drm/i915/i915_drv.c
2899
if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
sys/dev/drm/i915/i915_drv.c
2918
WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
sys/dev/drm/i915/i915_drv.h
3638
upper = I915_READ(upper_reg); \
sys/dev/drm/i915/i915_drv.h
3641
lower = I915_READ(lower_reg); \
sys/dev/drm/i915/i915_drv.h
3642
upper = I915_READ(upper_reg); \
sys/dev/drm/i915/i915_gem.c
5626
I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
sys/dev/drm/i915/i915_gem.c
5632
I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
sys/dev/drm/i915/i915_gem.c
5697
I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
sys/dev/drm/i915/i915_gem.c
5705
u32 temp = I915_READ(GEN7_MSG_CTL);
sys/dev/drm/i915/i915_gem.c
5709
u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
sys/dev/drm/i915/i915_gem.c
6193
I915_READ(vgtif_reg(avail_rs.fence_num));
sys/dev/drm/i915/i915_gem_fence_reg.c
572
if (I915_READ(DISP_ARB_CTL) &
sys/dev/drm/i915/i915_gem_fence_reg.c
582
dimm_c0 = I915_READ(MAD_DIMM_C0);
sys/dev/drm/i915/i915_gem_fence_reg.c
583
dimm_c1 = I915_READ(MAD_DIMM_C1);
sys/dev/drm/i915/i915_gem_fence_reg.c
623
dcc = I915_READ(DCC);
sys/dev/drm/i915/i915_gem_fence_reg.c
651
!(I915_READ(DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
sys/dev/drm/i915/i915_gem_gtt.c
1807
ecobits = I915_READ(GAC_ECO_BITS);
sys/dev/drm/i915/i915_gem_gtt.c
1810
ecochk = I915_READ(GAM_ECOCHK);
sys/dev/drm/i915/i915_gem_gtt.c
1830
ecobits = I915_READ(GAC_ECO_BITS);
sys/dev/drm/i915/i915_gem_gtt.c
1834
gab_ctl = I915_READ(GAB_CTL);
sys/dev/drm/i915/i915_gem_gtt.c
1837
ecochk = I915_READ(GAM_ECOCHK);
sys/dev/drm/i915/i915_gem_gtt.c
2244
I915_READ(GEN8_GAMW_ECO_DEV_RW_IA) |
sys/dev/drm/i915/i915_gem_gtt.c
2359
fault = I915_READ(RING_FAULT_REG(engine));
sys/dev/drm/i915/i915_gem_gtt.c
2376
u32 fault = I915_READ(GEN8_RING_FAULT_REG);
sys/dev/drm/i915/i915_gem_gtt.c
2382
fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
sys/dev/drm/i915/i915_gem_gtt.c
2383
fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
sys/dev/drm/i915/i915_gem_stolen.c
127
ggtt_start = I915_READ(PGTBL_CTL);
sys/dev/drm/i915/i915_gem_stolen.c
205
u32 reg_val = I915_READ(IS_GM45(dev_priv) ?
sys/dev/drm/i915/i915_gem_stolen.c
235
u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED);
sys/dev/drm/i915/i915_gem_stolen.c
267
u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED);
sys/dev/drm/i915/i915_gem_stolen.c
295
u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED);
sys/dev/drm/i915/i915_gem_stolen.c
321
u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED);
sys/dev/drm/i915/i915_gem_stolen.c
353
u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED);
sys/dev/drm/i915/i915_gpu_error.c
1128
error->fence[i] = I915_READ(FENCE_REG(i));
sys/dev/drm/i915/i915_gpu_error.c
1138
ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
sys/dev/drm/i915/i915_gpu_error.c
1139
ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
sys/dev/drm/i915/i915_gpu_error.c
1142
I915_READ(RING_SYNC_2(engine->mmio_base));
sys/dev/drm/i915/i915_gpu_error.c
1205
ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
sys/dev/drm/i915/i915_gpu_error.c
1207
ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
sys/dev/drm/i915/i915_gpu_error.c
1210
ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
sys/dev/drm/i915/i915_gpu_error.c
1215
ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
sys/dev/drm/i915/i915_gpu_error.c
1216
ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
sys/dev/drm/i915/i915_gpu_error.c
1217
ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
sys/dev/drm/i915/i915_gpu_error.c
1218
ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
sys/dev/drm/i915/i915_gpu_error.c
1219
ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
sys/dev/drm/i915/i915_gpu_error.c
1221
ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
sys/dev/drm/i915/i915_gpu_error.c
1222
ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
sys/dev/drm/i915/i915_gpu_error.c
1224
ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
sys/dev/drm/i915/i915_gpu_error.c
1226
ee->faddr = I915_READ(DMA_FADD_I8XX);
sys/dev/drm/i915/i915_gpu_error.c
1227
ee->ipeir = I915_READ(IPEIR);
sys/dev/drm/i915/i915_gpu_error.c
1228
ee->ipehr = I915_READ(IPEHR);
sys/dev/drm/i915/i915_gpu_error.c
1234
ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
sys/dev/drm/i915/i915_gpu_error.c
1271
ee->hws = I915_READ(mmio);
sys/dev/drm/i915/i915_gpu_error.c
1284
ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
sys/dev/drm/i915/i915_gpu_error.c
1288
I915_READ(RING_PP_DIR_BASE_READ(engine));
sys/dev/drm/i915/i915_gpu_error.c
1291
I915_READ(RING_PP_DIR_BASE(engine));
sys/dev/drm/i915/i915_gpu_error.c
1295
I915_READ(GEN8_RING_PDP_UDW(engine, i));
sys/dev/drm/i915/i915_gpu_error.c
1298
I915_READ(GEN8_RING_PDP_LDW(engine, i));
sys/dev/drm/i915/i915_gpu_error.c
1654
error->gtier[0] = I915_READ(GTIER);
sys/dev/drm/i915/i915_gpu_error.c
1655
error->ier = I915_READ(VLV_IER);
sys/dev/drm/i915/i915_gpu_error.c
1660
error->err_int = I915_READ(GEN7_ERR_INT);
sys/dev/drm/i915/i915_gpu_error.c
1663
error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
sys/dev/drm/i915/i915_gpu_error.c
1664
error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
sys/dev/drm/i915/i915_gpu_error.c
1669
error->gab_ctl = I915_READ(GAB_CTL);
sys/dev/drm/i915/i915_gpu_error.c
1670
error->gfx_mode = I915_READ(GFX_MODE);
sys/dev/drm/i915/i915_gpu_error.c
1678
error->derrmr = I915_READ(DERRMR);
sys/dev/drm/i915/i915_gpu_error.c
1679
error->error = I915_READ(ERROR_GEN6);
sys/dev/drm/i915/i915_gpu_error.c
1680
error->done_reg = I915_READ(DONE_REG);
sys/dev/drm/i915/i915_gpu_error.c
1684
error->ccid = I915_READ(CCID);
sys/dev/drm/i915/i915_gpu_error.c
1688
error->gam_ecochk = I915_READ(GAM_ECOCHK);
sys/dev/drm/i915/i915_gpu_error.c
1689
error->gac_eco = I915_READ(GAC_ECO_BITS);
sys/dev/drm/i915/i915_gpu_error.c
1694
error->ier = I915_READ(GEN8_DE_MISC_IER);
sys/dev/drm/i915/i915_gpu_error.c
1695
error->gtier[0] = I915_READ(GEN11_RENDER_COPY_INTR_ENABLE);
sys/dev/drm/i915/i915_gpu_error.c
1696
error->gtier[1] = I915_READ(GEN11_VCS_VECS_INTR_ENABLE);
sys/dev/drm/i915/i915_gpu_error.c
1697
error->gtier[2] = I915_READ(GEN11_GUC_SG_INTR_ENABLE);
sys/dev/drm/i915/i915_gpu_error.c
1698
error->gtier[3] = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
sys/dev/drm/i915/i915_gpu_error.c
1699
error->gtier[4] = I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE);
sys/dev/drm/i915/i915_gpu_error.c
1700
error->gtier[5] = I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE);
sys/dev/drm/i915/i915_gpu_error.c
1703
error->ier = I915_READ(GEN8_DE_MISC_IER);
sys/dev/drm/i915/i915_gpu_error.c
1705
error->gtier[i] = I915_READ(GEN8_GT_IER(i));
sys/dev/drm/i915/i915_gpu_error.c
1708
error->ier = I915_READ(DEIER);
sys/dev/drm/i915/i915_gpu_error.c
1709
error->gtier[0] = I915_READ(GTIER);
sys/dev/drm/i915/i915_gpu_error.c
1714
error->ier = I915_READ(IER);
sys/dev/drm/i915/i915_gpu_error.c
1716
error->eir = I915_READ(EIR);
sys/dev/drm/i915/i915_gpu_error.c
1717
error->pgtbl_er = I915_READ(PGTBL_ER);
sys/dev/drm/i915/i915_irq.c
1124
I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
sys/dev/drm/i915/i915_irq.c
1129
busy_up = I915_READ(RCPREVBSYTUPAVG);
sys/dev/drm/i915/i915_irq.c
1130
busy_down = I915_READ(RCPREVBSYTDNAVG);
sys/dev/drm/i915/i915_irq.c
1131
max_avg = I915_READ(RCBMAXAVG);
sys/dev/drm/i915/i915_irq.c
1132
min_avg = I915_READ(RCBMINAVG);
sys/dev/drm/i915/i915_irq.c
1229
ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
sys/dev/drm/i915/i915_irq.c
1230
ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
sys/dev/drm/i915/i915_irq.c
1392
misccpctl = I915_READ(GEN7_MISCCPCTL);
sys/dev/drm/i915/i915_irq.c
1407
error_status = I915_READ(reg);
sys/dev/drm/i915/i915_irq.c
171
u32 val = I915_READ(reg);
sys/dev/drm/i915/i915_irq.c
1789
I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
sys/dev/drm/i915/i915_irq.c
1797
I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
sys/dev/drm/i915/i915_irq.c
1798
I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
sys/dev/drm/i915/i915_irq.c
1799
I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
sys/dev/drm/i915/i915_irq.c
1800
I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
sys/dev/drm/i915/i915_irq.c
1801
I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
sys/dev/drm/i915/i915_irq.c
1810
res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
sys/dev/drm/i915/i915_irq.c
1815
res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
sys/dev/drm/i915/i915_irq.c
1820
I915_READ(PIPE_CRC_RES_RED(pipe)),
sys/dev/drm/i915/i915_irq.c
1821
I915_READ(PIPE_CRC_RES_GREEN(pipe)),
sys/dev/drm/i915/i915_irq.c
1822
I915_READ(PIPE_CRC_RES_BLUE(pipe)),
sys/dev/drm/i915/i915_irq.c
1919
pipe_stats[pipe] = I915_READ(reg) & status_mask;
sys/dev/drm/i915/i915_irq.c
2049
u32 tmp = I915_READ(PORT_HOTPLUG_STAT) & hotplug_status_mask;
sys/dev/drm/i915/i915_irq.c
2060
I915_READ(PORT_HOTPLUG_STAT));
sys/dev/drm/i915/i915_irq.c
2116
gt_iir = I915_READ(GTIIR);
sys/dev/drm/i915/i915_irq.c
2117
pm_iir = I915_READ(GEN6_PMIIR);
sys/dev/drm/i915/i915_irq.c
2118
iir = I915_READ(VLV_IIR);
sys/dev/drm/i915/i915_irq.c
2139
ier = I915_READ(VLV_IER);
sys/dev/drm/i915/i915_irq.c
2203
master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
sys/dev/drm/i915/i915_irq.c
2204
iir = I915_READ(VLV_IIR);
sys/dev/drm/i915/i915_irq.c
2225
ier = I915_READ(VLV_IER);
sys/dev/drm/i915/i915_irq.c
2277
dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
sys/dev/drm/i915/i915_irq.c
2330
I915_READ(FDI_RX_IIR(pipe)));
sys/dev/drm/i915/i915_irq.c
2347
u32 err_int = I915_READ(GEN7_ERR_INT);
sys/dev/drm/i915/i915_irq.c
235
val = I915_READ(PORT_HOTPLUG_EN);
sys/dev/drm/i915/i915_irq.c
2370
u32 serr_int = I915_READ(SERR_INT);
sys/dev/drm/i915/i915_irq.c
2413
I915_READ(FDI_RX_IIR(pipe)));
sys/dev/drm/i915/i915_irq.c
2428
dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
sys/dev/drm/i915/i915_irq.c
2440
dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
sys/dev/drm/i915/i915_irq.c
2466
dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
sys/dev/drm/i915/i915_irq.c
2477
dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
sys/dev/drm/i915/i915_irq.c
2498
dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
sys/dev/drm/i915/i915_irq.c
2539
u32 pch_iir = I915_READ(SDEIIR);
sys/dev/drm/i915/i915_irq.c
2567
u32 psr_iir = I915_READ(EDP_PSR_IIR);
sys/dev/drm/i915/i915_irq.c
2586
u32 pch_iir = I915_READ(SDEIIR);
sys/dev/drm/i915/i915_irq.c
2617
de_ier = I915_READ(DEIER);
sys/dev/drm/i915/i915_irq.c
2626
sde_ier = I915_READ(SDEIER);
sys/dev/drm/i915/i915_irq.c
2632
gt_iir = I915_READ(GTIIR);
sys/dev/drm/i915/i915_irq.c
2642
de_iir = I915_READ(DEIIR);
sys/dev/drm/i915/i915_irq.c
2653
u32 pm_iir = I915_READ(GEN6_PMIIR);
sys/dev/drm/i915/i915_irq.c
2677
dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
sys/dev/drm/i915/i915_irq.c
2696
dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL);
sys/dev/drm/i915/i915_irq.c
2707
dig_hotplug_reg = I915_READ(GEN11_TBT_HOTPLUG_CTL);
sys/dev/drm/i915/i915_irq.c
2729
iir = I915_READ(GEN8_DE_MISC_IIR);
sys/dev/drm/i915/i915_irq.c
2742
u32 psr_iir = I915_READ(EDP_PSR_IIR);
sys/dev/drm/i915/i915_irq.c
2757
iir = I915_READ(GEN11_DE_HPD_IIR);
sys/dev/drm/i915/i915_irq.c
2768
iir = I915_READ(GEN8_DE_PORT_IIR);
sys/dev/drm/i915/i915_irq.c
2828
iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
sys/dev/drm/i915/i915_irq.c
2865
iir = I915_READ(SDEIIR);
sys/dev/drm/i915/i915_irq.c
3219
I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER));
sys/dev/drm/i915/i915_irq.c
3222
I915_WRITE(IPEIR, I915_READ(IPEIR));
sys/dev/drm/i915/i915_irq.c
3224
I915_WRITE(IPEIR_I965, I915_READ(IPEIR_I965));
sys/dev/drm/i915/i915_irq.c
3226
I915_WRITE(EIR, I915_READ(EIR));
sys/dev/drm/i915/i915_irq.c
3227
eir = I915_READ(EIR);
sys/dev/drm/i915/i915_irq.c
3234
I915_WRITE(EMR, I915_READ(EMR) | eir);
sys/dev/drm/i915/i915_irq.c
3240
I915_READ(GEN8_RING_FAULT_REG) & ~RING_FAULT_VALID);
sys/dev/drm/i915/i915_irq.c
3248
I915_READ(RING_FAULT_REG(engine)) &
sys/dev/drm/i915/i915_irq.c
3498
WARN_ON(I915_READ(SDEIER) != 0);
sys/dev/drm/i915/i915_irq.c
3518
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
sys/dev/drm/i915/i915_irq.c
3752
hotplug = I915_READ(PCH_PORT_HOTPLUG);
sys/dev/drm/i915/i915_irq.c
3789
hotplug = I915_READ(SHOTPLUG_CTL_DDI);
sys/dev/drm/i915/i915_irq.c
3794
hotplug = I915_READ(SHOTPLUG_CTL_TC);
sys/dev/drm/i915/i915_irq.c
3818
hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
sys/dev/drm/i915/i915_irq.c
3825
hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
sys/dev/drm/i915/i915_irq.c
3841
val = I915_READ(GEN11_DE_HPD_IMR);
sys/dev/drm/i915/i915_irq.c
3858
val = I915_READ(SOUTH_CHICKEN1);
sys/dev/drm/i915/i915_irq.c
3865
hotplug = I915_READ(PCH_PORT_HOTPLUG);
sys/dev/drm/i915/i915_irq.c
3872
hotplug = I915_READ(PCH_PORT_HOTPLUG2);
sys/dev/drm/i915/i915_irq.c
3898
hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
sys/dev/drm/i915/i915_irq.c
3936
hotplug = I915_READ(PCH_PORT_HOTPLUG);
sys/dev/drm/i915/i915_irq.c
4290
WARN_ON(I915_READ(SDEIER) != 0);
sys/dev/drm/i915/i915_irq.c
4424
*eir = I915_READ(EIR);
sys/dev/drm/i915/i915_irq.c
4428
*eir_stuck = I915_READ(EIR);
sys/dev/drm/i915/i915_irq.c
4442
emr = I915_READ(EMR);
sys/dev/drm/i915/i915_irq.c
4508
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
sys/dev/drm/i915/i915_irq.c
4579
iir = I915_READ(IIR);
sys/dev/drm/i915/i915_irq.c
4620
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
sys/dev/drm/i915/i915_irq.c
4727
iir = I915_READ(IIR);
sys/dev/drm/i915/i915_irq.c
499
WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
sys/dev/drm/i915/i915_irq.c
551
WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
sys/dev/drm/i915/i915_irq.c
594
old_val = I915_READ(GEN8_DE_PORT_IMR);
sys/dev/drm/i915/i915_irq.c
648
uint32_t sdeimr = I915_READ(SDEIMR);
sys/dev/drm/i915/i915_irq.c
876
return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
sys/dev/drm/i915/i915_perf.c
1082
oastatus1 = I915_READ(GEN7_OASTATUS1);
sys/dev/drm/i915/i915_perf.c
1123
oastatus1 = I915_READ(GEN7_OASTATUS1);
sys/dev/drm/i915/i915_perf.c
1581
I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
sys/dev/drm/i915/i915_perf.c
1583
I915_WRITE(GEN6_UCGCTL1, (I915_READ(GEN6_UCGCTL1) |
sys/dev/drm/i915/i915_perf.c
1619
I915_WRITE(GEN6_UCGCTL1, (I915_READ(GEN6_UCGCTL1) &
sys/dev/drm/i915/i915_perf.c
1621
I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) |
sys/dev/drm/i915/i915_perf.c
1624
I915_WRITE(GDT_CHICKEN_BITS, (I915_READ(GDT_CHICKEN_BITS) &
sys/dev/drm/i915/i915_perf.c
1829
I915_WRITE(GDT_CHICKEN_BITS, (I915_READ(GDT_CHICKEN_BITS) &
sys/dev/drm/i915/i915_perf.c
1840
I915_READ(RPM_CONFIG1) & ~GEN10_GT_NOA_ENABLE);
sys/dev/drm/i915/i915_perf.c
419
return I915_READ(GEN8_OATAILPTR) & GEN8_OATAILPTR_MASK;
sys/dev/drm/i915/i915_perf.c
424
u32 oastatus1 = I915_READ(GEN7_OASTATUS1);
sys/dev/drm/i915/i915_perf.c
871
oastatus = I915_READ(GEN8_OASTATUS);
sys/dev/drm/i915/i915_perf.c
903
oastatus = I915_READ(GEN8_OASTATUS);
sys/dev/drm/i915/i915_suspend.c
36
dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
sys/dev/drm/i915/i915_suspend.c
40
dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
sys/dev/drm/i915/i915_suspend.c
74
dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
sys/dev/drm/i915/i915_suspend.c
77
dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
sys/dev/drm/i915/i915_suspend.c
82
dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
sys/dev/drm/i915/i915_suspend.c
83
dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
sys/dev/drm/i915/i915_suspend.c
86
dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
sys/dev/drm/i915/i915_suspend.c
89
dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
sys/dev/drm/i915/i915_suspend.c
92
dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
sys/dev/drm/i915/i915_suspend.c
93
dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
sys/dev/drm/i915/i915_suspend.c
96
dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
sys/dev/drm/i915/i915_sysfs.c
274
I915_READ(GEN6_RPSTAT1)));
sys/dev/drm/i915/i915_vgpu.c
209
mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base));
sys/dev/drm/i915/i915_vgpu.c
210
mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size));
sys/dev/drm/i915/i915_vgpu.c
211
unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base));
sys/dev/drm/i915/i915_vgpu.c
212
unmappable_size = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size));
sys/dev/drm/i915/icl_dsi.c
102
tmp = I915_READ(ICL_PORT_CL_DW10(port));
sys/dev/drm/i915/icl_dsi.c
65
tmp = I915_READ(ICL_DSI_IO_MODECTL(port));
sys/dev/drm/i915/intel_audio.c
237
tmp = I915_READ(reg_eldv);
sys/dev/drm/i915/intel_audio.c
243
tmp = I915_READ(reg_elda);
sys/dev/drm/i915/intel_audio.c
248
if (I915_READ(reg_edid) != *((const u32 *)eld + i))
sys/dev/drm/i915/intel_audio.c
263
tmp = I915_READ(G4X_AUD_VID_DID);
sys/dev/drm/i915/intel_audio.c
270
tmp = I915_READ(G4X_AUD_CNTL_ST);
sys/dev/drm/i915/intel_audio.c
288
tmp = I915_READ(G4X_AUD_VID_DID);
sys/dev/drm/i915/intel_audio.c
300
tmp = I915_READ(G4X_AUD_CNTL_ST);
sys/dev/drm/i915/intel_audio.c
310
tmp = I915_READ(G4X_AUD_CNTL_ST);
sys/dev/drm/i915/intel_audio.c
335
tmp = I915_READ(HSW_AUD_CFG(pipe));
sys/dev/drm/i915/intel_audio.c
349
tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe));
sys/dev/drm/i915/intel_audio.c
377
tmp = I915_READ(HSW_AUD_CFG(pipe));
sys/dev/drm/i915/intel_audio.c
400
tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe));
sys/dev/drm/i915/intel_audio.c
430
tmp = I915_READ(HSW_AUD_CFG(pipe));
sys/dev/drm/i915/intel_audio.c
440
tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
sys/dev/drm/i915/intel_audio.c
466
tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
sys/dev/drm/i915/intel_audio.c
479
tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
sys/dev/drm/i915/intel_audio.c
489
tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
sys/dev/drm/i915/intel_audio.c
528
tmp = I915_READ(aud_config);
sys/dev/drm/i915/intel_audio.c
540
tmp = I915_READ(aud_cntrl_st2);
sys/dev/drm/i915/intel_audio.c
593
tmp = I915_READ(aud_cntrl_st2);
sys/dev/drm/i915/intel_audio.c
598
tmp = I915_READ(aud_cntl_st);
sys/dev/drm/i915/intel_audio.c
608
tmp = I915_READ(aud_cntrl_st2);
sys/dev/drm/i915/intel_audio.c
613
tmp = I915_READ(aud_config);
sys/dev/drm/i915/intel_audio.c
771
tmp = I915_READ(HSW_AUD_CHICKENBIT);
sys/dev/drm/i915/intel_audio.c
777
tmp = I915_READ(HSW_AUD_CHICKENBIT);
sys/dev/drm/i915/intel_cdclk.c
1044
cdclk_ctl = I915_READ(CDCLK_CTL);
sys/dev/drm/i915/intel_cdclk.c
1091
if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
sys/dev/drm/i915/intel_cdclk.c
1108
cdctl = I915_READ(CDCLK_CTL);
sys/dev/drm/i915/intel_cdclk.c
1263
val = I915_READ(BXT_DE_PLL_ENABLE);
sys/dev/drm/i915/intel_cdclk.c
1270
val = I915_READ(BXT_DE_PLL_CTL);
sys/dev/drm/i915/intel_cdclk.c
1287
divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
sys/dev/drm/i915/intel_cdclk.c
1337
val = I915_READ(BXT_DE_PLL_CTL);
sys/dev/drm/i915/intel_cdclk.c
1460
cdctl = I915_READ(CDCLK_CTL);
sys/dev/drm/i915/intel_cdclk.c
1575
if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
sys/dev/drm/i915/intel_cdclk.c
1582
val = I915_READ(BXT_DE_PLL_ENABLE);
sys/dev/drm/i915/intel_cdclk.c
1605
divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
sys/dev/drm/i915/intel_cdclk.c
1634
val = I915_READ(BXT_DE_PLL_ENABLE);
sys/dev/drm/i915/intel_cdclk.c
1639
if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
sys/dev/drm/i915/intel_cdclk.c
1657
if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
sys/dev/drm/i915/intel_cdclk.c
1767
cdctl = I915_READ(CDCLK_CTL);
sys/dev/drm/i915/intel_cdclk.c
1916
val = I915_READ(SKL_DSSM);
sys/dev/drm/i915/intel_cdclk.c
1932
val = I915_READ(BXT_DE_PLL_ENABLE);
sys/dev/drm/i915/intel_cdclk.c
1946
val = I915_READ(CDCLK_CTL);
sys/dev/drm/i915/intel_cdclk.c
1982
val = I915_READ(CDCLK_CTL);
sys/dev/drm/i915/intel_cdclk.c
237
tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
sys/dev/drm/i915/intel_cdclk.c
2569
u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
sys/dev/drm/i915/intel_cdclk.c
2601
if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
sys/dev/drm/i915/intel_cdclk.c
2653
if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
sys/dev/drm/i915/intel_cdclk.c
2677
if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
sys/dev/drm/i915/intel_cdclk.c
2698
return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
sys/dev/drm/i915/intel_cdclk.c
2713
clkcfg = I915_READ(CLKCFG);
sys/dev/drm/i915/intel_cdclk.c
406
uint32_t lcpll = I915_READ(LCPLL_CTL);
sys/dev/drm/i915/intel_cdclk.c
411
else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
sys/dev/drm/i915/intel_cdclk.c
515
WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
sys/dev/drm/i915/intel_cdclk.c
673
uint32_t lcpll = I915_READ(LCPLL_CTL);
sys/dev/drm/i915/intel_cdclk.c
678
else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
sys/dev/drm/i915/intel_cdclk.c
704
if (WARN((I915_READ(LCPLL_CTL) &
sys/dev/drm/i915/intel_cdclk.c
721
val = I915_READ(LCPLL_CTL);
sys/dev/drm/i915/intel_cdclk.c
729
if (wait_for_us(I915_READ(LCPLL_CTL) &
sys/dev/drm/i915/intel_cdclk.c
733
val = I915_READ(LCPLL_CTL);
sys/dev/drm/i915/intel_cdclk.c
756
val = I915_READ(LCPLL_CTL);
sys/dev/drm/i915/intel_cdclk.c
760
if (wait_for_us((I915_READ(LCPLL_CTL) &
sys/dev/drm/i915/intel_cdclk.c
823
val = I915_READ(LCPLL1_CTL);
sys/dev/drm/i915/intel_cdclk.c
830
val = I915_READ(DPLL_CTRL1);
sys/dev/drm/i915/intel_cdclk.c
867
cdctl = I915_READ(CDCLK_CTL);
sys/dev/drm/i915/intel_cdclk.c
948
val = I915_READ(DPLL_CTRL1);
sys/dev/drm/i915/intel_cdclk.c
963
I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
sys/dev/drm/i915/intel_cdclk.c
978
I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
sys/dev/drm/i915/intel_crt.c
1048
dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
sys/dev/drm/i915/intel_crt.c
106
tmp = I915_READ(crt->adpa_reg);
sys/dev/drm/i915/intel_crt.c
424
save_adpa = adpa = I915_READ(crt->adpa_reg);
sys/dev/drm/i915/intel_crt.c
446
adpa = I915_READ(crt->adpa_reg);
sys/dev/drm/i915/intel_crt.c
480
save_adpa = adpa = I915_READ(crt->adpa_reg);
sys/dev/drm/i915/intel_crt.c
496
adpa = I915_READ(crt->adpa_reg);
sys/dev/drm/i915/intel_crt.c
546
stat = I915_READ(PORT_HOTPLUG_STAT);
sys/dev/drm/i915/intel_crt.c
653
save_bclrpat = I915_READ(bclrpat_reg);
sys/dev/drm/i915/intel_crt.c
654
save_vtotal = I915_READ(vtotal_reg);
sys/dev/drm/i915/intel_crt.c
655
vblank = I915_READ(vblank_reg);
sys/dev/drm/i915/intel_crt.c
667
uint32_t pipeconf = I915_READ(pipeconf_reg);
sys/dev/drm/i915/intel_crt.c
688
uint32_t vsync = I915_READ(vsync_reg);
sys/dev/drm/i915/intel_crt.c
706
while (I915_READ(pipe_dsl_reg) >= vactive)
sys/dev/drm/i915/intel_crt.c
708
while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
sys/dev/drm/i915/intel_crt.c
71
val = I915_READ(adpa_reg);
sys/dev/drm/i915/intel_crt.c
721
} while ((I915_READ(pipe_dsl_reg) == dsl));
sys/dev/drm/i915/intel_crt.c
892
adpa = I915_READ(crt->adpa_reg);
sys/dev/drm/i915/intel_crt.c
943
adpa = I915_READ(adpa_reg);
sys/dev/drm/i915/intel_crt.c
955
if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0)
sys/dev/drm/i915/intel_csr.c
228
val = I915_READ(DC_STATE_DEBUG);
sys/dev/drm/i915/intel_ddi.c
1035
if (I915_READ(reg) & DDI_BUF_IS_IDLE)
sys/dev/drm/i915/intel_ddi.c
1182
temp = I915_READ(FDI_RX_MISC(PIPE_A));
sys/dev/drm/i915/intel_ddi.c
1190
temp = I915_READ(DP_TP_STATUS(PORT_E));
sys/dev/drm/i915/intel_ddi.c
1209
temp = I915_READ(DDI_BUF_CTL(PORT_E));
sys/dev/drm/i915/intel_ddi.c
1215
temp = I915_READ(DP_TP_CTL(PORT_E));
sys/dev/drm/i915/intel_ddi.c
1224
temp = I915_READ(FDI_RX_MISC(PIPE_A));
sys/dev/drm/i915/intel_ddi.c
1279
wrpll = I915_READ(reg);
sys/dev/drm/i915/intel_ddi.c
1316
cfgcr1_val = I915_READ(cfgcr1_reg);
sys/dev/drm/i915/intel_ddi.c
1317
cfgcr2_val = I915_READ(cfgcr2_reg);
sys/dev/drm/i915/intel_ddi.c
1373
cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
sys/dev/drm/i915/intel_ddi.c
1374
cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
sys/dev/drm/i915/intel_ddi.c
1376
cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
sys/dev/drm/i915/intel_ddi.c
1377
cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
sys/dev/drm/i915/intel_ddi.c
1433
u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
sys/dev/drm/i915/intel_ddi.c
1461
mg_pll_div0 = I915_READ(MG_PLL_DIV0(port));
sys/dev/drm/i915/intel_ddi.c
1462
mg_clktop_hsclkctl = I915_READ(MG_CLKTOP2_HSCLKCTL(port));
sys/dev/drm/i915/intel_ddi.c
1464
m1 = I915_READ(MG_PLL_DIV1(port)) & MG_PLL_DIV1_FBPREDIV_MASK;
sys/dev/drm/i915/intel_ddi.c
1565
cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
sys/dev/drm/i915/intel_ddi.c
1619
dpll_ctl1 = I915_READ(DPLL_CTRL1);
sys/dev/drm/i915/intel_ddi.c
1683
pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
sys/dev/drm/i915/intel_ddi.c
1798
temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
sys/dev/drm/i915/intel_ddi.c
1898
uint32_t val = I915_READ(reg);
sys/dev/drm/i915/intel_ddi.c
1930
tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
sys/dev/drm/i915/intel_ddi.c
1967
tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
sys/dev/drm/i915/intel_ddi.c
2017
tmp = I915_READ(DDI_BUF_CTL(port));
sys/dev/drm/i915/intel_ddi.c
2023
tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
sys/dev/drm/i915/intel_ddi.c
2046
tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
sys/dev/drm/i915/intel_ddi.c
2064
tmp = I915_READ(BXT_PHY_CTL(port));
sys/dev/drm/i915/intel_ddi.c
2151
tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
sys/dev/drm/i915/intel_ddi.c
2311
val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
sys/dev/drm/i915/intel_ddi.c
2317
val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
sys/dev/drm/i915/intel_ddi.c
2329
val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
sys/dev/drm/i915/intel_ddi.c
2340
val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
sys/dev/drm/i915/intel_ddi.c
2347
val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
sys/dev/drm/i915/intel_ddi.c
2376
val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
sys/dev/drm/i915/intel_ddi.c
2391
val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
sys/dev/drm/i915/intel_ddi.c
2402
val = I915_READ(CNL_PORT_CL1CM_DW5);
sys/dev/drm/i915/intel_ddi.c
2407
val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
sys/dev/drm/i915/intel_ddi.c
2415
val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
sys/dev/drm/i915/intel_ddi.c
2438
val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
sys/dev/drm/i915/intel_ddi.c
2444
val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
sys/dev/drm/i915/intel_ddi.c
2458
val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
sys/dev/drm/i915/intel_ddi.c
2470
val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
sys/dev/drm/i915/intel_ddi.c
2504
val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
sys/dev/drm/i915/intel_ddi.c
2519
val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
sys/dev/drm/i915/intel_ddi.c
2530
val = I915_READ(ICL_PORT_CL_DW5(port));
sys/dev/drm/i915/intel_ddi.c
2535
val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
sys/dev/drm/i915/intel_ddi.c
2543
val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
sys/dev/drm/i915/intel_ddi.c
2569
val = I915_READ(MG_TX1_LINK_PARAMS(port, ln));
sys/dev/drm/i915/intel_ddi.c
2573
val = I915_READ(MG_TX2_LINK_PARAMS(port, ln));
sys/dev/drm/i915/intel_ddi.c
2580
val = I915_READ(MG_TX1_SWINGCTRL(port, ln));
sys/dev/drm/i915/intel_ddi.c
2586
val = I915_READ(MG_TX2_SWINGCTRL(port, ln));
sys/dev/drm/i915/intel_ddi.c
2595
val = I915_READ(MG_TX1_DRVCTRL(port, ln));
sys/dev/drm/i915/intel_ddi.c
2605
val = I915_READ(MG_TX2_DRVCTRL(port, ln));
sys/dev/drm/i915/intel_ddi.c
2624
val = I915_READ(MG_CLKHUB(port, ln));
sys/dev/drm/i915/intel_ddi.c
2634
val = I915_READ(MG_TX1_DCC(port, ln));
sys/dev/drm/i915/intel_ddi.c
2644
val = I915_READ(MG_TX2_DCC(port, ln));
sys/dev/drm/i915/intel_ddi.c
2657
val = I915_READ(MG_TX1_PISO_READLOAD(port, ln));
sys/dev/drm/i915/intel_ddi.c
2661
val = I915_READ(MG_TX2_PISO_READLOAD(port, ln));
sys/dev/drm/i915/intel_ddi.c
2773
val = I915_READ(DPCLKA_CFGCR0_ICL);
sys/dev/drm/i915/intel_ddi.c
2810
I915_READ(DPCLKA_CFGCR0_ICL) |
sys/dev/drm/i915/intel_ddi.c
2834
val = I915_READ(DPCLKA_CFGCR0);
sys/dev/drm/i915/intel_ddi.c
2844
val = I915_READ(DPCLKA_CFGCR0);
sys/dev/drm/i915/intel_ddi.c
2849
val = I915_READ(DPLL_CTRL2);
sys/dev/drm/i915/intel_ddi.c
2874
I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
sys/dev/drm/i915/intel_ddi.c
2877
I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
sys/dev/drm/i915/intel_ddi.c
3009
val = I915_READ(DDI_BUF_CTL(port));
sys/dev/drm/i915/intel_ddi.c
3016
val = I915_READ(DP_TP_CTL(port));
sys/dev/drm/i915/intel_ddi.c
3117
val = I915_READ(FDI_RX_CTL(PIPE_A));
sys/dev/drm/i915/intel_ddi.c
3124
val = I915_READ(FDI_RX_MISC(PIPE_A));
sys/dev/drm/i915/intel_ddi.c
3129
val = I915_READ(FDI_RX_CTL(PIPE_A));
sys/dev/drm/i915/intel_ddi.c
3133
val = I915_READ(FDI_RX_CTL(PIPE_A));
sys/dev/drm/i915/intel_ddi.c
3190
val = I915_READ(CHICKEN_TRANS(transcoder));
sys/dev/drm/i915/intel_ddi.c
3303
if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
sys/dev/drm/i915/intel_ddi.c
3304
val = I915_READ(DDI_BUF_CTL(port));
sys/dev/drm/i915/intel_ddi.c
3311
val = I915_READ(DP_TP_CTL(port));
sys/dev/drm/i915/intel_ddi.c
3349
return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
sys/dev/drm/i915/intel_ddi.c
3375
temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
sys/dev/drm/i915/intel_ddi.c
3743
if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
sys/dev/drm/i915/intel_ddi.c
3824
intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
sys/dev/drm/i915/intel_ddi.c
3827
intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
sys/dev/drm/i915/intel_ddi.c
809
u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
sys/dev/drm/i915/intel_ddi.c
830
u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
sys/dev/drm/i915/intel_ddi.c
851
u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
sys/dev/drm/i915/intel_ddi.c
877
u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
sys/dev/drm/i915/intel_device_info.c
173
s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
sys/dev/drm/i915/intel_device_info.c
174
ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
sys/dev/drm/i915/intel_device_info.c
176
eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK);
sys/dev/drm/i915/intel_device_info.c
203
const u32 fuse2 = I915_READ(GEN8_FUSE2);
sys/dev/drm/i915/intel_device_info.c
227
eu_en = ~I915_READ(GEN8_EU_DISABLE0);
sys/dev/drm/i915/intel_device_info.c
232
eu_en = ~I915_READ(GEN8_EU_DISABLE1);
sys/dev/drm/i915/intel_device_info.c
239
eu_en = ~I915_READ(GEN8_EU_DISABLE2);
sys/dev/drm/i915/intel_device_info.c
246
eu_en = ~I915_READ(GEN10_EU_DISABLE3);
sys/dev/drm/i915/intel_device_info.c
282
fuse = I915_READ(CHV_FUSE_GT);
sys/dev/drm/i915/intel_device_info.c
338
fuse2 = I915_READ(GEN8_FUSE2);
sys/dev/drm/i915/intel_device_info.c
365
eu_disable = I915_READ(GEN9_EU_DISABLE(s));
sys/dev/drm/i915/intel_device_info.c
440
fuse2 = I915_READ(GEN8_FUSE2);
sys/dev/drm/i915/intel_device_info.c
454
eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
sys/dev/drm/i915/intel_device_info.c
455
eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
sys/dev/drm/i915/intel_device_info.c
456
((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
sys/dev/drm/i915/intel_device_info.c
458
eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
sys/dev/drm/i915/intel_device_info.c
459
((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
sys/dev/drm/i915/intel_device_info.c
549
fuse1 = I915_READ(HSW_PAVP_FUSE1);
sys/dev/drm/i915/intel_device_info.c
584
u32 ts_override = I915_READ(GEN9_TIMESTAMP_OVERRIDE);
sys/dev/drm/i915/intel_device_info.c
668
u32 ctc_reg = I915_READ(CTC_MODE);
sys/dev/drm/i915/intel_device_info.c
686
u32 ctc_reg = I915_READ(CTC_MODE);
sys/dev/drm/i915/intel_device_info.c
697
u32 rpm_config_reg = I915_READ(RPM_CONFIG0);
sys/dev/drm/i915/intel_device_info.c
785
u32 fuse_strap = I915_READ(FUSE_STRAP);
sys/dev/drm/i915/intel_device_info.c
786
u32 sfuse_strap = I915_READ(SFUSE_STRAP);
sys/dev/drm/i915/intel_device_info.c
808
u32 dfsm = I915_READ(SKL_DFSM);
sys/dev/drm/i915/intel_device_info.c
882
media_fuse = I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE);
sys/dev/drm/i915/intel_display.c
10233
val = I915_READ(CURCNTR(plane->pipe));
sys/dev/drm/i915/intel_display.c
10553
u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
sys/dev/drm/i915/intel_display.c
1057
line1 = I915_READ(reg) & line_mask;
sys/dev/drm/i915/intel_display.c
1059
line2 = I915_READ(reg) & line_mask;
sys/dev/drm/i915/intel_display.c
1112
val = I915_READ(DPLL(pipe));
sys/dev/drm/i915/intel_display.c
1144
u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
sys/dev/drm/i915/intel_display.c
1147
u32 val = I915_READ(FDI_TX_CTL(pipe));
sys/dev/drm/i915/intel_display.c
1163
val = I915_READ(FDI_RX_CTL(pipe));
sys/dev/drm/i915/intel_display.c
1185
val = I915_READ(FDI_TX_CTL(pipe));
sys/dev/drm/i915/intel_display.c
1195
val = I915_READ(FDI_RX_CTL(pipe));
sys/dev/drm/i915/intel_display.c
1216
port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
sys/dev/drm/i915/intel_display.c
1243
port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
sys/dev/drm/i915/intel_display.c
1249
val = I915_READ(pp_reg);
sys/dev/drm/i915/intel_display.c
1273
u32 val = I915_READ(PIPECONF(cpu_transcoder));
sys/dev/drm/i915/intel_display.c
1322
val = I915_READ(PCH_TRANSCONF(pipe));
sys/dev/drm/i915/intel_display.c
14209
if ((I915_READ(DP_A) & DP_DETECTED) == 0)
sys/dev/drm/i915/intel_display.c
14212
if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
sys/dev/drm/i915/intel_display.c
14230
I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
sys/dev/drm/i915/intel_display.c
14234
if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
sys/dev/drm/i915/intel_display.c
14260
u32 val = I915_READ(PP_CONTROL(pps_idx));
sys/dev/drm/i915/intel_display.c
14325
found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
sys/dev/drm/i915/intel_display.c
14332
found = I915_READ(SFUSE_STRAP);
sys/dev/drm/i915/intel_display.c
14358
if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
sys/dev/drm/i915/intel_display.c
14363
if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
sys/dev/drm/i915/intel_display.c
14367
if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
sys/dev/drm/i915/intel_display.c
14370
if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
sys/dev/drm/i915/intel_display.c
14373
if (I915_READ(PCH_DP_C) & DP_DETECTED)
sys/dev/drm/i915/intel_display.c
14376
if (I915_READ(PCH_DP_D) & DP_DETECTED)
sys/dev/drm/i915/intel_display.c
14398
if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
sys/dev/drm/i915/intel_display.c
14400
if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
sys/dev/drm/i915/intel_display.c
14405
if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
sys/dev/drm/i915/intel_display.c
14407
if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
sys/dev/drm/i915/intel_display.c
14416
if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
sys/dev/drm/i915/intel_display.c
14418
if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
sys/dev/drm/i915/intel_display.c
14426
if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
sys/dev/drm/i915/intel_display.c
14440
if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
sys/dev/drm/i915/intel_display.c
14445
if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
sys/dev/drm/i915/intel_display.c
14455
if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
sys/dev/drm/i915/intel_display.c
1488
WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
sys/dev/drm/i915/intel_display.c
15264
I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
sys/dev/drm/i915/intel_display.c
1532
I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
sys/dev/drm/i915/intel_display.c
15369
bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
sys/dev/drm/i915/intel_display.c
15498
dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
sys/dev/drm/i915/intel_display.c
15555
WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
sys/dev/drm/i915/intel_display.c
15556
WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
sys/dev/drm/i915/intel_display.c
15557
WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
sys/dev/drm/i915/intel_display.c
15558
WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE);
sys/dev/drm/i915/intel_display.c
15559
WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE);
sys/dev/drm/i915/intel_display.c
15639
I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
sys/dev/drm/i915/intel_display.c
15777
if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
sys/dev/drm/i915/intel_display.c
1578
I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
sys/dev/drm/i915/intel_display.c
1580
I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
sys/dev/drm/i915/intel_display.c
16013
I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
sys/dev/drm/i915/intel_display.c
16022
I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
sys/dev/drm/i915/intel_display.c
16326
error->power_well_driver = I915_READ(HSW_PWR_WELL_CTL2);
sys/dev/drm/i915/intel_display.c
16335
error->cursor[i].control = I915_READ(CURCNTR(i));
sys/dev/drm/i915/intel_display.c
16336
error->cursor[i].position = I915_READ(CURPOS(i));
sys/dev/drm/i915/intel_display.c
16337
error->cursor[i].base = I915_READ(CURBASE(i));
sys/dev/drm/i915/intel_display.c
16339
error->plane[i].control = I915_READ(DSPCNTR(i));
sys/dev/drm/i915/intel_display.c
16340
error->plane[i].stride = I915_READ(DSPSTRIDE(i));
sys/dev/drm/i915/intel_display.c
16342
error->plane[i].size = I915_READ(DSPSIZE(i));
sys/dev/drm/i915/intel_display.c
16343
error->plane[i].pos = I915_READ(DSPPOS(i));
sys/dev/drm/i915/intel_display.c
16346
error->plane[i].addr = I915_READ(DSPADDR(i));
sys/dev/drm/i915/intel_display.c
16348
error->plane[i].surface = I915_READ(DSPSURF(i));
sys/dev/drm/i915/intel_display.c
16349
error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
sys/dev/drm/i915/intel_display.c
16352
error->pipe[i].source = I915_READ(PIPESRC(i));
sys/dev/drm/i915/intel_display.c
16355
error->pipe[i].stat = I915_READ(PIPESTAT(i));
sys/dev/drm/i915/intel_display.c
16374
error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
sys/dev/drm/i915/intel_display.c
16375
error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
sys/dev/drm/i915/intel_display.c
16376
error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
sys/dev/drm/i915/intel_display.c
16377
error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
sys/dev/drm/i915/intel_display.c
16378
error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
sys/dev/drm/i915/intel_display.c
16379
error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
sys/dev/drm/i915/intel_display.c
16380
error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
sys/dev/drm/i915/intel_display.c
1666
I915_READ(dpll_reg) & port_mask, expected_mask);
sys/dev/drm/i915/intel_display.c
1688
val = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
1694
val = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
1695
pipeconf_val = I915_READ(PIPECONF(pipe));
sys/dev/drm/i915/intel_display.c
1737
val = I915_READ(TRANS_CHICKEN2(PIPE_A));
sys/dev/drm/i915/intel_display.c
1742
pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
sys/dev/drm/i915/intel_display.c
1773
val = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
1785
val = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
1795
val = I915_READ(LPT_TRANSCONF);
sys/dev/drm/i915/intel_display.c
1805
val = I915_READ(TRANS_CHICKEN2(PIPE_A));
sys/dev/drm/i915/intel_display.c
1855
val = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
1894
val = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
3494
val = I915_READ(DSPCNTR(i9xx_plane));
sys/dev/drm/i915/intel_display.c
3958
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
3969
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
3985
I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
sys/dev/drm/i915/intel_display.c
4005
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4009
I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4014
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4022
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4037
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4051
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4057
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4067
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4103
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4113
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4127
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4142
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4152
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4169
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4180
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4195
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4205
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4236
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4245
I915_READ(FDI_RX_IIR(pipe)));
sys/dev/drm/i915/intel_display.c
4251
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4257
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4265
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4278
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4288
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4292
(I915_READ(reg) & FDI_RX_BIT_LOCK)) {
sys/dev/drm/i915/intel_display.c
4307
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4313
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4323
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4327
(I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
sys/dev/drm/i915/intel_display.c
4353
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4356
temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
sys/dev/drm/i915/intel_display.c
4363
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4371
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4390
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4395
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4402
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4421
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4426
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4428
temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
sys/dev/drm/i915/intel_display.c
4440
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4446
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4456
temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
sys/dev/drm/i915/intel_display.c
4589
if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
sys/dev/drm/i915/intel_display.c
4626
I915_READ(HTOTAL(cpu_transcoder)));
sys/dev/drm/i915/intel_display.c
4628
I915_READ(HBLANK(cpu_transcoder)));
sys/dev/drm/i915/intel_display.c
4630
I915_READ(HSYNC(cpu_transcoder)));
sys/dev/drm/i915/intel_display.c
4633
I915_READ(VTOTAL(cpu_transcoder)));
sys/dev/drm/i915/intel_display.c
4635
I915_READ(VBLANK(cpu_transcoder)));
sys/dev/drm/i915/intel_display.c
4637
I915_READ(VSYNC(cpu_transcoder)));
sys/dev/drm/i915/intel_display.c
4639
I915_READ(VSYNCSHIFT(cpu_transcoder)));
sys/dev/drm/i915/intel_display.c
4647
temp = I915_READ(SOUTH_CHICKEN1);
sys/dev/drm/i915/intel_display.c
4651
WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
sys/dev/drm/i915/intel_display.c
4652
WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
sys/dev/drm/i915/intel_display.c
4740
I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
sys/dev/drm/i915/intel_display.c
4750
temp = I915_READ(PCH_DPLL_SEL);
sys/dev/drm/i915/intel_display.c
4781
u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
sys/dev/drm/i915/intel_display.c
4785
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
4830
temp = I915_READ(dslreg);
sys/dev/drm/i915/intel_display.c
4832
if (wait_for(I915_READ(dslreg) != temp, 5)) {
sys/dev/drm/i915/intel_display.c
4833
if (wait_for(I915_READ(dslreg) != temp, 5))
sys/dev/drm/i915/intel_display.c
531
I915_READ(CLKGATE_DIS_PSL(pipe)) &
sys/dev/drm/i915/intel_display.c
5726
u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
sys/dev/drm/i915/intel_display.c
5827
pipe_chicken = I915_READ(PIPE_CHICKEN(pipe));
sys/dev/drm/i915/intel_display.c
5927
temp = I915_READ(reg);
sys/dev/drm/i915/intel_display.c
5934
temp = I915_READ(PCH_DPLL_SEL);
sys/dev/drm/i915/intel_display.c
5993
WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
sys/dev/drm/i915/intel_display.c
6248
I915_READ(PFIT_CONTROL));
sys/dev/drm/i915/intel_display.c
7460
I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
sys/dev/drm/i915/intel_display.c
7486
tmp = I915_READ(HTOTAL(cpu_transcoder));
sys/dev/drm/i915/intel_display.c
7489
tmp = I915_READ(HBLANK(cpu_transcoder));
sys/dev/drm/i915/intel_display.c
7492
tmp = I915_READ(HSYNC(cpu_transcoder));
sys/dev/drm/i915/intel_display.c
7496
tmp = I915_READ(VTOTAL(cpu_transcoder));
sys/dev/drm/i915/intel_display.c
7499
tmp = I915_READ(VBLANK(cpu_transcoder));
sys/dev/drm/i915/intel_display.c
7502
tmp = I915_READ(VSYNC(cpu_transcoder));
sys/dev/drm/i915/intel_display.c
7506
if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
sys/dev/drm/i915/intel_display.c
7520
tmp = I915_READ(PIPESRC(crtc->pipe));
sys/dev/drm/i915/intel_display.c
7560
pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
sys/dev/drm/i915/intel_display.c
7805
tmp = I915_READ(PFIT_CONTROL);
sys/dev/drm/i915/intel_display.c
7819
pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
sys/dev/drm/i915/intel_display.c
7879
val = I915_READ(DSPCNTR(i9xx_plane));
sys/dev/drm/i915/intel_display.c
7900
offset = I915_READ(DSPOFFSET(i9xx_plane));
sys/dev/drm/i915/intel_display.c
7901
base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
sys/dev/drm/i915/intel_display.c
7904
offset = I915_READ(DSPTILEOFF(i9xx_plane));
sys/dev/drm/i915/intel_display.c
7906
offset = I915_READ(DSPLINOFF(i9xx_plane));
sys/dev/drm/i915/intel_display.c
7907
base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
sys/dev/drm/i915/intel_display.c
7909
base = I915_READ(DSPADDR(i9xx_plane));
sys/dev/drm/i915/intel_display.c
7913
val = I915_READ(PIPESRC(pipe));
sys/dev/drm/i915/intel_display.c
7917
val = I915_READ(DSPSTRIDE(i9xx_plane));
sys/dev/drm/i915/intel_display.c
7983
tmp = I915_READ(PIPECONF(crtc->pipe));
sys/dev/drm/i915/intel_display.c
8021
tmp = I915_READ(DPLL_MD(crtc->pipe));
sys/dev/drm/i915/intel_display.c
8028
tmp = I915_READ(DPLL(crtc->pipe));
sys/dev/drm/i915/intel_display.c
8038
pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
sys/dev/drm/i915/intel_display.c
8048
pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
sys/dev/drm/i915/intel_display.c
8049
pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
sys/dev/drm/i915/intel_display.c
8119
u32 temp = I915_READ(PCH_DPLL(i));
sys/dev/drm/i915/intel_display.c
8139
val = I915_READ(PCH_DREF_CONTROL);
sys/dev/drm/i915/intel_display.c
8251
tmp = I915_READ(SOUTH_CHICKEN2);
sys/dev/drm/i915/intel_display.c
8255
if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
sys/dev/drm/i915/intel_display.c
8259
tmp = I915_READ(SOUTH_CHICKEN2);
sys/dev/drm/i915/intel_display.c
8263
if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
sys/dev/drm/i915/intel_display.c
8790
m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
sys/dev/drm/i915/intel_display.c
8791
m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
sys/dev/drm/i915/intel_display.c
8792
m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
sys/dev/drm/i915/intel_display.c
8794
m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
sys/dev/drm/i915/intel_display.c
8795
m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
sys/dev/drm/i915/intel_display.c
8808
m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
sys/dev/drm/i915/intel_display.c
8809
m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
sys/dev/drm/i915/intel_display.c
8810
m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
sys/dev/drm/i915/intel_display.c
8812
m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
sys/dev/drm/i915/intel_display.c
8813
m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
sys/dev/drm/i915/intel_display.c
8821
m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
sys/dev/drm/i915/intel_display.c
8822
m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
sys/dev/drm/i915/intel_display.c
8823
m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
sys/dev/drm/i915/intel_display.c
8825
m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
sys/dev/drm/i915/intel_display.c
8826
m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
sys/dev/drm/i915/intel_display.c
8830
m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
sys/dev/drm/i915/intel_display.c
8831
m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
sys/dev/drm/i915/intel_display.c
8832
m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
sys/dev/drm/i915/intel_display.c
8834
m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
sys/dev/drm/i915/intel_display.c
8835
m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
sys/dev/drm/i915/intel_display.c
8870
ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
sys/dev/drm/i915/intel_display.c
8874
pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
sys/dev/drm/i915/intel_display.c
8875
pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
sys/dev/drm/i915/intel_display.c
8918
val = I915_READ(PLANE_CTL(pipe, plane_id));
sys/dev/drm/i915/intel_display.c
8926
alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
sys/dev/drm/i915/intel_display.c
8986
base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
sys/dev/drm/i915/intel_display.c
8989
offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
sys/dev/drm/i915/intel_display.c
8991
val = I915_READ(PLANE_SIZE(pipe, plane_id));
sys/dev/drm/i915/intel_display.c
8995
val = I915_READ(PLANE_STRIDE(pipe, plane_id));
sys/dev/drm/i915/intel_display.c
9022
tmp = I915_READ(PF_CTL(crtc->pipe));
sys/dev/drm/i915/intel_display.c
9026
pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
sys/dev/drm/i915/intel_display.c
9027
pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
sys/dev/drm/i915/intel_display.c
9056
tmp = I915_READ(PIPECONF(crtc->pipe));
sys/dev/drm/i915/intel_display.c
9080
if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
sys/dev/drm/i915/intel_display.c
9086
tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
sys/dev/drm/i915/intel_display.c
9099
tmp = I915_READ(PCH_DPLL_SEL);
sys/dev/drm/i915/intel_display.c
9145
I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL2),
sys/dev/drm/i915/intel_display.c
9147
I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
sys/dev/drm/i915/intel_display.c
9148
I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
sys/dev/drm/i915/intel_display.c
9149
I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
sys/dev/drm/i915/intel_display.c
9150
I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
sys/dev/drm/i915/intel_display.c
9151
I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
sys/dev/drm/i915/intel_display.c
9154
I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
sys/dev/drm/i915/intel_display.c
9156
I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
sys/dev/drm/i915/intel_display.c
9158
I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
sys/dev/drm/i915/intel_display.c
9160
I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
sys/dev/drm/i915/intel_display.c
9174
return I915_READ(D_COMP_HSW);
sys/dev/drm/i915/intel_display.c
9176
return I915_READ(D_COMP_BDW);
sys/dev/drm/i915/intel_display.c
9208
val = I915_READ(LCPLL_CTL);
sys/dev/drm/i915/intel_display.c
9214
if (wait_for_us(I915_READ(LCPLL_CTL) &
sys/dev/drm/i915/intel_display.c
9218
val = I915_READ(LCPLL_CTL);
sys/dev/drm/i915/intel_display.c
9238
val = I915_READ(LCPLL_CTL);
sys/dev/drm/i915/intel_display.c
9253
val = I915_READ(LCPLL_CTL);
sys/dev/drm/i915/intel_display.c
9276
val = I915_READ(LCPLL_CTL);
sys/dev/drm/i915/intel_display.c
9286
val = I915_READ(LCPLL_CTL);
sys/dev/drm/i915/intel_display.c
9290
if (wait_for_us((I915_READ(LCPLL_CTL) &
sys/dev/drm/i915/intel_display.c
9331
val = I915_READ(SOUTH_DSPCLK_GATE_D);
sys/dev/drm/i915/intel_display.c
9350
val = I915_READ(SOUTH_DSPCLK_GATE_D);
sys/dev/drm/i915/intel_display.c
9383
temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
sys/dev/drm/i915/intel_display.c
9403
temp = I915_READ(DPCLKA_CFGCR0_ICL) &
sys/dev/drm/i915/intel_display.c
9461
temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
sys/dev/drm/i915/intel_display.c
9475
uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
sys/dev/drm/i915/intel_display.c
9525
tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
sys/dev/drm/i915/intel_display.c
9553
tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
sys/dev/drm/i915/intel_display.c
9591
tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
sys/dev/drm/i915/intel_display.c
9595
tmp = I915_READ(MIPI_CTRL(port));
sys/dev/drm/i915/intel_display.c
9614
tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
sys/dev/drm/i915/intel_display.c
9641
(port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
sys/dev/drm/i915/intel_display.c
9644
tmp = I915_READ(FDI_RX_CTL(PIPE_A));
sys/dev/drm/i915/intel_display.c
9688
I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
sys/dev/drm/i915/intel_display.c
9691
u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
sys/dev/drm/i915/intel_display.c
9718
pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE;
sys/dev/drm/i915/intel_display.c
9732
I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
sys/dev/drm/i915/intel_display.c
9997
ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
sys/dev/drm/i915/intel_dp.c
1072
pp_div = I915_READ(pp_div_reg);
sys/dev/drm/i915/intel_dp.c
1096
return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
sys/dev/drm/i915/intel_dp.c
1109
return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
sys/dev/drm/i915/intel_dp.c
1123
I915_READ(_pp_stat_reg(intel_dp)),
sys/dev/drm/i915/intel_dp.c
1124
I915_READ(_pp_ctrl_reg(intel_dp)));
sys/dev/drm/i915/intel_dp.c
1305
const u32 status = I915_READ(ch_ctl);
sys/dev/drm/i915/intel_dp.c
1411
intel_dp_unpack_aux(I915_READ(ch_data[i >> 2]),
sys/dev/drm/i915/intel_dp.c
183
lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
sys/dev/drm/i915/intel_dp.c
2166
intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
sys/dev/drm/i915/intel_dp.c
2190
trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
sys/dev/drm/i915/intel_dp.c
2243
I915_READ(pp_stat_reg),
sys/dev/drm/i915/intel_dp.c
2244
I915_READ(pp_ctrl_reg));
sys/dev/drm/i915/intel_dp.c
2250
I915_READ(pp_stat_reg),
sys/dev/drm/i915/intel_dp.c
2251
I915_READ(pp_ctrl_reg));
sys/dev/drm/i915/intel_dp.c
2312
control = I915_READ(_pp_ctrl_reg(intel_dp));
sys/dev/drm/i915/intel_dp.c
2362
I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
sys/dev/drm/i915/intel_dp.c
237
ln0 = I915_READ(MG_DP_MODE(port, 0));
sys/dev/drm/i915/intel_dp.c
238
ln1 = I915_READ(MG_DP_MODE(port, 1));
sys/dev/drm/i915/intel_dp.c
2426
I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
sys/dev/drm/i915/intel_dp.c
245
lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
sys/dev/drm/i915/intel_dp.c
2701
bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
sys/dev/drm/i915/intel_dp.c
2712
bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
sys/dev/drm/i915/intel_dp.c
2840
u32 val = I915_READ(TRANS_DP_CTL(p));
sys/dev/drm/i915/intel_dp.c
2863
val = I915_READ(dp_reg);
sys/dev/drm/i915/intel_dp.c
2913
tmp = I915_READ(intel_dp->output_reg);
sys/dev/drm/i915/intel_dp.c
2918
u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
sys/dev/drm/i915/intel_dp.c
2952
if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
sys/dev/drm/i915/intel_dp.c
305
val = I915_READ(mg_regs[i]);
sys/dev/drm/i915/intel_dp.c
3075
uint32_t temp = I915_READ(DP_TP_CTL(port));
sys/dev/drm/i915/intel_dp.c
314
val = I915_READ(MG_MISC_SUS0(tc_port));
sys/dev/drm/i915/intel_dp.c
3174
uint32_t dp_reg = I915_READ(intel_dp->output_reg);
sys/dev/drm/i915/intel_dp.c
338
val = I915_READ(mg_regs[i]);
sys/dev/drm/i915/intel_dp.c
347
val = I915_READ(MG_MISC_SUS0(tc_port));
sys/dev/drm/i915/intel_dp.c
3800
val = I915_READ(DP_TP_CTL(port));
sys/dev/drm/i915/intel_dp.c
3835
if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
sys/dev/drm/i915/intel_dp.c
399
u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
sys/dev/drm/i915/intel_dp.c
4623
return I915_READ(SDEISR) & bit;
sys/dev/drm/i915/intel_dp.c
4646
return I915_READ(SDEISR) & bit;
sys/dev/drm/i915/intel_dp.c
4665
return I915_READ(SDEISR) & bit;
sys/dev/drm/i915/intel_dp.c
4688
return I915_READ(PORT_HOTPLUG_STAT) & bit;
sys/dev/drm/i915/intel_dp.c
4711
return I915_READ(PORT_HOTPLUG_STAT) & bit;
sys/dev/drm/i915/intel_dp.c
4719
return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
sys/dev/drm/i915/intel_dp.c
4729
return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
sys/dev/drm/i915/intel_dp.c
4739
return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
sys/dev/drm/i915/intel_dp.c
4749
return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
sys/dev/drm/i915/intel_dp.c
4774
return I915_READ(GEN8_DE_PORT_ISR) & bit;
sys/dev/drm/i915/intel_dp.c
4782
return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port);
sys/dev/drm/i915/intel_dp.c
4848
val = I915_READ(PORT_TX_DFLEXDPPMS);
sys/dev/drm/i915/intel_dp.c
4858
val = I915_READ(PORT_TX_DFLEXDPCSSS);
sys/dev/drm/i915/intel_dp.c
4869
!(I915_READ(PORT_TX_DFLEXDPSP) & TC_LIVE_STATE_TC(tc_port))) {
sys/dev/drm/i915/intel_dp.c
4871
val = I915_READ(PORT_TX_DFLEXDPCSSS);
sys/dev/drm/i915/intel_dp.c
4898
val = I915_READ(PORT_TX_DFLEXDPCSSS);
sys/dev/drm/i915/intel_dp.c
4923
is_legacy = I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port);
sys/dev/drm/i915/intel_dp.c
4929
dpsp = I915_READ(PORT_TX_DFLEXDPSP);
sys/dev/drm/i915/intel_dp.c
5610
intel_dp->DP = I915_READ(intel_dp->output_reg);
sys/dev/drm/i915/intel_dp.c
5785
pp_on = I915_READ(regs.pp_on);
sys/dev/drm/i915/intel_dp.c
5786
pp_off = I915_READ(regs.pp_off);
sys/dev/drm/i915/intel_dp.c
5790
pp_div = I915_READ(regs.pp_div);
sys/dev/drm/i915/intel_dp.c
5980
pp_div = I915_READ(regs.pp_ctrl);
sys/dev/drm/i915/intel_dp.c
6022
I915_READ(regs.pp_on),
sys/dev/drm/i915/intel_dp.c
6023
I915_READ(regs.pp_off),
sys/dev/drm/i915/intel_dp.c
6026
(I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
sys/dev/drm/i915/intel_dp.c
6027
I915_READ(regs.pp_div));
sys/dev/drm/i915/intel_dp.c
6119
val = I915_READ(reg);
sys/dev/drm/i915/intel_dp.c
6591
intel_dp->DP = I915_READ(intel_dp->output_reg);
sys/dev/drm/i915/intel_dp.c
6667
u32 temp = I915_READ(PEG_BAND_GAP_DATA);
sys/dev/drm/i915/intel_dp.c
719
if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
sys/dev/drm/i915/intel_dp.c
730
DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
sys/dev/drm/i915/intel_dp.c
740
pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
sys/dev/drm/i915/intel_dp.c
891
return I915_READ(PP_STATUS(pipe)) & PP_ON;
sys/dev/drm/i915/intel_dp.c
897
return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
sys/dev/drm/i915/intel_dp.c
914
u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
sys/dev/drm/i915/intel_dp_mst.c
256
temp = I915_READ(DP_TP_STATUS(port));
sys/dev/drm/i915/intel_dpio_phy.c
277
val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch));
sys/dev/drm/i915/intel_dpio_phy.c
281
val = I915_READ(BXT_PORT_TX_DW2_LN0(phy, ch));
sys/dev/drm/i915/intel_dpio_phy.c
286
val = I915_READ(BXT_PORT_TX_DW3_LN0(phy, ch));
sys/dev/drm/i915/intel_dpio_phy.c
296
val = I915_READ(BXT_PORT_TX_DW4_LN0(phy, ch));
sys/dev/drm/i915/intel_dpio_phy.c
301
val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch));
sys/dev/drm/i915/intel_dpio_phy.c
313
if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))
sys/dev/drm/i915/intel_dpio_phy.c
316
if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
sys/dev/drm/i915/intel_dpio_phy.c
324
if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
sys/dev/drm/i915/intel_dpio_phy.c
336
u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
sys/dev/drm/i915/intel_dpio_phy.c
374
val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
sys/dev/drm/i915/intel_dpio_phy.c
393
val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
sys/dev/drm/i915/intel_dpio_phy.c
398
val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
sys/dev/drm/i915/intel_dpio_phy.c
404
val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
sys/dev/drm/i915/intel_dpio_phy.c
410
val = I915_READ(BXT_PORT_CL2CM_DW6(phy));
sys/dev/drm/i915/intel_dpio_phy.c
432
val = I915_READ(BXT_PORT_REF_DW8(phy));
sys/dev/drm/i915/intel_dpio_phy.c
440
val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
sys/dev/drm/i915/intel_dpio_phy.c
452
val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
sys/dev/drm/i915/intel_dpio_phy.c
456
val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
sys/dev/drm/i915/intel_dpio_phy.c
496
val = I915_READ(reg);
sys/dev/drm/i915/intel_dpio_phy.c
599
u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));
sys/dev/drm/i915/intel_dpio_phy.c
627
u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));
sys/dev/drm/i915/intel_dpll_mgr.c
1006
val = I915_READ(regs[id].ctl);
sys/dev/drm/i915/intel_dpll_mgr.c
1010
val = I915_READ(DPLL_CTRL1);
sys/dev/drm/i915/intel_dpll_mgr.c
1015
hw_state->cfgcr1 = I915_READ(regs[id].cfgcr1);
sys/dev/drm/i915/intel_dpll_mgr.c
1016
hw_state->cfgcr2 = I915_READ(regs[id].cfgcr2);
sys/dev/drm/i915/intel_dpll_mgr.c
1041
val = I915_READ(regs[id].ctl);
sys/dev/drm/i915/intel_dpll_mgr.c
1045
val = I915_READ(DPLL_CTRL1);
sys/dev/drm/i915/intel_dpll_mgr.c
1453
temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
sys/dev/drm/i915/intel_dpll_mgr.c
1458
temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
sys/dev/drm/i915/intel_dpll_mgr.c
1462
if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
sys/dev/drm/i915/intel_dpll_mgr.c
1468
temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
sys/dev/drm/i915/intel_dpll_mgr.c
1473
temp = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch));
sys/dev/drm/i915/intel_dpll_mgr.c
1479
temp = I915_READ(BXT_PORT_PLL(phy, ch, 0));
sys/dev/drm/i915/intel_dpll_mgr.c
1485
temp = I915_READ(BXT_PORT_PLL(phy, ch, 1));
sys/dev/drm/i915/intel_dpll_mgr.c
1491
temp = I915_READ(BXT_PORT_PLL(phy, ch, 2));
sys/dev/drm/i915/intel_dpll_mgr.c
1497
temp = I915_READ(BXT_PORT_PLL(phy, ch, 3));
sys/dev/drm/i915/intel_dpll_mgr.c
1503
temp = I915_READ(BXT_PORT_PLL(phy, ch, 6));
sys/dev/drm/i915/intel_dpll_mgr.c
1511
temp = I915_READ(BXT_PORT_PLL(phy, ch, 8));
sys/dev/drm/i915/intel_dpll_mgr.c
1516
temp = I915_READ(BXT_PORT_PLL(phy, ch, 9));
sys/dev/drm/i915/intel_dpll_mgr.c
1521
temp = I915_READ(BXT_PORT_PLL(phy, ch, 10));
sys/dev/drm/i915/intel_dpll_mgr.c
1528
temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
sys/dev/drm/i915/intel_dpll_mgr.c
1536
temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
sys/dev/drm/i915/intel_dpll_mgr.c
1541
if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),
sys/dev/drm/i915/intel_dpll_mgr.c
1546
temp = I915_READ(BXT_PORT_TX_DW5_LN0(phy, ch));
sys/dev/drm/i915/intel_dpll_mgr.c
1555
temp = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch));
sys/dev/drm/i915/intel_dpll_mgr.c
1568
temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
sys/dev/drm/i915/intel_dpll_mgr.c
1574
temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
sys/dev/drm/i915/intel_dpll_mgr.c
1578
if (wait_for_us(!(I915_READ(BXT_PORT_PLL_ENABLE(port)) &
sys/dev/drm/i915/intel_dpll_mgr.c
1601
val = I915_READ(BXT_PORT_PLL_ENABLE(port));
sys/dev/drm/i915/intel_dpll_mgr.c
1605
hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch));
sys/dev/drm/i915/intel_dpll_mgr.c
1608
hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
sys/dev/drm/i915/intel_dpll_mgr.c
1611
hw_state->pll0 = I915_READ(BXT_PORT_PLL(phy, ch, 0));
sys/dev/drm/i915/intel_dpll_mgr.c
1614
hw_state->pll1 = I915_READ(BXT_PORT_PLL(phy, ch, 1));
sys/dev/drm/i915/intel_dpll_mgr.c
1617
hw_state->pll2 = I915_READ(BXT_PORT_PLL(phy, ch, 2));
sys/dev/drm/i915/intel_dpll_mgr.c
1620
hw_state->pll3 = I915_READ(BXT_PORT_PLL(phy, ch, 3));
sys/dev/drm/i915/intel_dpll_mgr.c
1623
hw_state->pll6 = I915_READ(BXT_PORT_PLL(phy, ch, 6));
sys/dev/drm/i915/intel_dpll_mgr.c
1628
hw_state->pll8 = I915_READ(BXT_PORT_PLL(phy, ch, 8));
sys/dev/drm/i915/intel_dpll_mgr.c
1631
hw_state->pll9 = I915_READ(BXT_PORT_PLL(phy, ch, 9));
sys/dev/drm/i915/intel_dpll_mgr.c
1634
hw_state->pll10 = I915_READ(BXT_PORT_PLL(phy, ch, 10));
sys/dev/drm/i915/intel_dpll_mgr.c
1643
hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch));
sys/dev/drm/i915/intel_dpll_mgr.c
1644
if (I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)
sys/dev/drm/i915/intel_dpll_mgr.c
1647
I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch)));
sys/dev/drm/i915/intel_dpll_mgr.c
1883
uint32_t val = I915_READ(LCPLL_CTL);
sys/dev/drm/i915/intel_dpll_mgr.c
1972
val = I915_READ(CNL_DPLL_ENABLE(id));
sys/dev/drm/i915/intel_dpll_mgr.c
2013
val = I915_READ(CNL_DPLL_ENABLE(id));
sys/dev/drm/i915/intel_dpll_mgr.c
2061
val = I915_READ(CNL_DPLL_ENABLE(id));
sys/dev/drm/i915/intel_dpll_mgr.c
2083
val = I915_READ(CNL_DPLL_ENABLE(id));
sys/dev/drm/i915/intel_dpll_mgr.c
2109
val = I915_READ(CNL_DPLL_ENABLE(id));
sys/dev/drm/i915/intel_dpll_mgr.c
2113
val = I915_READ(CNL_DPLL_CFGCR0(id));
sys/dev/drm/i915/intel_dpll_mgr.c
2118
hw_state->cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(id));
sys/dev/drm/i915/intel_dpll_mgr.c
2564
cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
sys/dev/drm/i915/intel_dpll_mgr.c
2565
cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
sys/dev/drm/i915/intel_dpll_mgr.c
2964
val = I915_READ(icl_pll_id_to_enable_reg(id));
sys/dev/drm/i915/intel_dpll_mgr.c
2972
hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
sys/dev/drm/i915/intel_dpll_mgr.c
2973
hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
sys/dev/drm/i915/intel_dpll_mgr.c
2980
hw_state->mg_refclkin_ctl = I915_READ(MG_REFCLKIN_CTL(port));
sys/dev/drm/i915/intel_dpll_mgr.c
2984
I915_READ(MG_CLKTOP2_CORECLKCTL1(port));
sys/dev/drm/i915/intel_dpll_mgr.c
2989
I915_READ(MG_CLKTOP2_HSCLKCTL(port));
sys/dev/drm/i915/intel_dpll_mgr.c
2996
hw_state->mg_pll_div0 = I915_READ(MG_PLL_DIV0(port));
sys/dev/drm/i915/intel_dpll_mgr.c
2997
hw_state->mg_pll_div1 = I915_READ(MG_PLL_DIV1(port));
sys/dev/drm/i915/intel_dpll_mgr.c
2998
hw_state->mg_pll_lf = I915_READ(MG_PLL_LF(port));
sys/dev/drm/i915/intel_dpll_mgr.c
2999
hw_state->mg_pll_frac_lock = I915_READ(MG_PLL_FRAC_LOCK(port));
sys/dev/drm/i915/intel_dpll_mgr.c
3000
hw_state->mg_pll_ssc = I915_READ(MG_PLL_SSC(port));
sys/dev/drm/i915/intel_dpll_mgr.c
3002
hw_state->mg_pll_bias = I915_READ(MG_PLL_BIAS(port));
sys/dev/drm/i915/intel_dpll_mgr.c
3004
I915_READ(MG_PLL_TDC_COLDST_BIAS(port));
sys/dev/drm/i915/intel_dpll_mgr.c
3051
val = I915_READ(MG_REFCLKIN_CTL(port));
sys/dev/drm/i915/intel_dpll_mgr.c
3056
val = I915_READ(MG_CLKTOP2_CORECLKCTL1(port));
sys/dev/drm/i915/intel_dpll_mgr.c
3061
val = I915_READ(MG_CLKTOP2_HSCLKCTL(port));
sys/dev/drm/i915/intel_dpll_mgr.c
3075
val = I915_READ(MG_PLL_BIAS(port));
sys/dev/drm/i915/intel_dpll_mgr.c
3080
val = I915_READ(MG_PLL_TDC_COLDST_BIAS(port));
sys/dev/drm/i915/intel_dpll_mgr.c
3095
val = I915_READ(enable_reg);
sys/dev/drm/i915/intel_dpll_mgr.c
3129
val = I915_READ(enable_reg);
sys/dev/drm/i915/intel_dpll_mgr.c
3155
val = I915_READ(enable_reg);
sys/dev/drm/i915/intel_dpll_mgr.c
3165
val = I915_READ(enable_reg);
sys/dev/drm/i915/intel_dpll_mgr.c
352
val = I915_READ(PCH_DPLL(id));
sys/dev/drm/i915/intel_dpll_mgr.c
354
hw_state->fp0 = I915_READ(PCH_FP0(id));
sys/dev/drm/i915/intel_dpll_mgr.c
355
hw_state->fp1 = I915_READ(PCH_FP1(id));
sys/dev/drm/i915/intel_dpll_mgr.c
378
val = I915_READ(PCH_DREF_CONTROL);
sys/dev/drm/i915/intel_dpll_mgr.c
499
val = I915_READ(WRPLL_CTL(id));
sys/dev/drm/i915/intel_dpll_mgr.c
509
val = I915_READ(SPLL_CTL);
sys/dev/drm/i915/intel_dpll_mgr.c
524
val = I915_READ(WRPLL_CTL(id));
sys/dev/drm/i915/intel_dpll_mgr.c
541
val = I915_READ(SPLL_CTL);
sys/dev/drm/i915/intel_dpll_mgr.c
933
val = I915_READ(DPLL_CTRL1);
sys/dev/drm/i915/intel_dpll_mgr.c
959
I915_READ(regs[id].ctl) | LCPLL_PLL_ENABLE);
sys/dev/drm/i915/intel_dpll_mgr.c
983
I915_READ(regs[id].ctl) & ~LCPLL_PLL_ENABLE);
sys/dev/drm/i915/intel_dvo.c
129
tmp = I915_READ(intel_dvo->dev.dvo_reg);
sys/dev/drm/i915/intel_dvo.c
144
tmp = I915_READ(intel_dvo->dev.dvo_reg);
sys/dev/drm/i915/intel_dvo.c
160
tmp = I915_READ(intel_dvo->dev.dvo_reg);
sys/dev/drm/i915/intel_dvo.c
182
u32 temp = I915_READ(dvo_reg);
sys/dev/drm/i915/intel_dvo.c
186
I915_READ(dvo_reg);
sys/dev/drm/i915/intel_dvo.c
196
u32 temp = I915_READ(dvo_reg);
sys/dev/drm/i915/intel_dvo.c
203
I915_READ(dvo_reg);
sys/dev/drm/i915/intel_dvo.c
276
dvo_val = I915_READ(dvo_reg) &
sys/dev/drm/i915/intel_dvo.c
478
dpll[pipe] = I915_READ(DPLL(pipe));
sys/dev/drm/i915/intel_engine_cs.c
1289
drm_printf(m, "\tCCID: 0x%08x\n", I915_READ(CCID));
sys/dev/drm/i915/intel_engine_cs.c
1291
I915_READ(RING_START(engine->mmio_base)));
sys/dev/drm/i915/intel_engine_cs.c
1293
I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR);
sys/dev/drm/i915/intel_engine_cs.c
1295
I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR);
sys/dev/drm/i915/intel_engine_cs.c
1297
I915_READ(RING_CTL(engine->mmio_base)),
sys/dev/drm/i915/intel_engine_cs.c
1298
I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
sys/dev/drm/i915/intel_engine_cs.c
1301
I915_READ(RING_MI_MODE(engine->mmio_base)),
sys/dev/drm/i915/intel_engine_cs.c
1302
I915_READ(RING_MI_MODE(engine->mmio_base)) & (MODE_IDLE) ? " [idle]" : "");
sys/dev/drm/i915/intel_engine_cs.c
1311
I915_READ(RING_SYNC_0(engine->mmio_base)));
sys/dev/drm/i915/intel_engine_cs.c
1313
I915_READ(RING_SYNC_1(engine->mmio_base)));
sys/dev/drm/i915/intel_engine_cs.c
1316
I915_READ(RING_SYNC_2(engine->mmio_base)));
sys/dev/drm/i915/intel_engine_cs.c
1329
addr = I915_READ(RING_DMA_FADD(engine->mmio_base));
sys/dev/drm/i915/intel_engine_cs.c
1331
addr = I915_READ(DMA_FADD_I8XX);
sys/dev/drm/i915/intel_engine_cs.c
1336
I915_READ(RING_IPEIR(engine->mmio_base)));
sys/dev/drm/i915/intel_engine_cs.c
1338
I915_READ(RING_IPEHR(engine->mmio_base)));
sys/dev/drm/i915/intel_engine_cs.c
1340
drm_printf(m, "\tIPEIR: 0x%08x\n", I915_READ(IPEIR));
sys/dev/drm/i915/intel_engine_cs.c
1341
drm_printf(m, "\tIPEHR: 0x%08x\n", I915_READ(IPEHR));
sys/dev/drm/i915/intel_engine_cs.c
1350
I915_READ(RING_EXECLIST_STATUS_LO(engine)),
sys/dev/drm/i915/intel_engine_cs.c
1351
I915_READ(RING_EXECLIST_STATUS_HI(engine)));
sys/dev/drm/i915/intel_engine_cs.c
1358
GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine))),
sys/dev/drm/i915/intel_engine_cs.c
1373
I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
sys/dev/drm/i915/intel_engine_cs.c
1375
I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
sys/dev/drm/i915/intel_engine_cs.c
1400
I915_READ(RING_PP_DIR_BASE(engine)));
sys/dev/drm/i915/intel_engine_cs.c
1402
I915_READ(RING_PP_DIR_BASE_READ(engine)));
sys/dev/drm/i915/intel_engine_cs.c
1404
I915_READ(RING_PP_DIR_DCLV(engine)));
sys/dev/drm/i915/intel_engine_cs.c
214
cxt_size = I915_READ(GEN7_CXT_SIZE);
sys/dev/drm/i915/intel_engine_cs.c
218
cxt_size = I915_READ(CXT_SIZE);
sys/dev/drm/i915/intel_engine_cs.c
694
acthd = I915_READ(RING_ACTHD(engine->mmio_base));
sys/dev/drm/i915/intel_engine_cs.c
696
acthd = I915_READ(ACTHD);
sys/dev/drm/i915/intel_engine_cs.c
710
bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
sys/dev/drm/i915/intel_engine_cs.c
853
instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
sys/dev/drm/i915/intel_engine_cs.c
858
instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);
sys/dev/drm/i915/intel_engine_cs.c
869
instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
sys/dev/drm/i915/intel_engine_cs.c
874
instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);
sys/dev/drm/i915/intel_engine_cs.c
875
instdone->sampler[0][0] = I915_READ(GEN7_SAMPLER_INSTDONE);
sys/dev/drm/i915/intel_engine_cs.c
876
instdone->row[0][0] = I915_READ(GEN7_ROW_INSTDONE);
sys/dev/drm/i915/intel_engine_cs.c
882
instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
sys/dev/drm/i915/intel_engine_cs.c
886
instdone->slice_common = I915_READ(GEN4_INSTDONE1);
sys/dev/drm/i915/intel_engine_cs.c
890
instdone->instdone = I915_READ(GEN2_INSTDONE);
sys/dev/drm/i915/intel_fbc.c
101
fbc_ctl = I915_READ(FBC_CONTROL);
sys/dev/drm/i915/intel_fbc.c
150
fbc_ctl = I915_READ(FBC_CONTROL);
sys/dev/drm/i915/intel_fbc.c
162
return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
sys/dev/drm/i915/intel_fbc.c
192
dpfc_ctl = I915_READ(DPFC_CONTROL);
sys/dev/drm/i915/intel_fbc.c
201
return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
sys/dev/drm/i915/intel_fbc.c
266
dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
sys/dev/drm/i915/intel_fbc.c
275
return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
sys/dev/drm/i915/intel_fbc.c
286
u32 val = I915_READ(CHICKEN_MISC_4);
sys/dev/drm/i915/intel_fbc.c
334
I915_READ(ILK_DISPLAY_CHICKEN1) |
sys/dev/drm/i915/intel_fbc.c
339
I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) |
sys/dev/drm/i915/intel_fifo_underrun.c
121
if (old && I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS)
sys/dev/drm/i915/intel_fifo_underrun.c
143
uint32_t err_int = I915_READ(GEN7_ERR_INT);
sys/dev/drm/i915/intel_fifo_underrun.c
173
I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
sys/dev/drm/i915/intel_fifo_underrun.c
209
uint32_t serr_int = I915_READ(SERR_INT);
sys/dev/drm/i915/intel_fifo_underrun.c
241
if (old && I915_READ(SERR_INT) &
sys/dev/drm/i915/intel_fifo_underrun.c
95
if ((I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)
sys/dev/drm/i915/intel_guc.c
449
response_buf[i] = I915_READ(guc_send_reg(guc, i + 1));
sys/dev/drm/i915/intel_guc.c
480
val = I915_READ(SOFT_SCRATCH(15));
sys/dev/drm/i915/intel_guc_fw.c
120
I915_READ(GEN7_MISCCPCTL)));
sys/dev/drm/i915/intel_guc_fw.c
202
u32 val = I915_READ(GUC_STATUS);
sys/dev/drm/i915/intel_guc_submission.c
218
if (wait_for_us(!(I915_READ(GEN8_DRBREGL(db_id)) & GEN8_DRB_VALID), 10))
sys/dev/drm/i915/intel_guc_submission.c
886
drbregl = I915_READ(GEN8_DRBREGL(db_id));
sys/dev/drm/i915/intel_hangcheck.c
87
ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
sys/dev/drm/i915/intel_hdcp.c
389
if (!(I915_READ(HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) {
sys/dev/drm/i915/intel_hdcp.c
520
an.reg[0] = I915_READ(PORT_HDCP_ANLO(port));
sys/dev/drm/i915/intel_hdcp.c
521
an.reg[1] = I915_READ(PORT_HDCP_ANHI(port));
sys/dev/drm/i915/intel_hdcp.c
560
if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
sys/dev/drm/i915/intel_hdcp.c
591
if (!wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
sys/dev/drm/i915/intel_hdcp.c
598
I915_READ(PORT_HDCP_STATUS(port)));
sys/dev/drm/i915/intel_hdcp.c
844
if (!(I915_READ(PORT_HDCP_STATUS(port)) & HDCP_STATUS_ENC)) {
sys/dev/drm/i915/intel_hdcp.c
847
I915_READ(PORT_HDCP_STATUS(port)));
sys/dev/drm/i915/intel_hdcp.c
89
val = I915_READ(HDCP_KEY_STATUS);
sys/dev/drm/i915/intel_hdcp.c
98
if (!(I915_READ(HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE))
sys/dev/drm/i915/intel_hdmi.c
1114
if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
sys/dev/drm/i915/intel_hdmi.c
1117
I915_READ(PORT_HDCP_STATUS(port)));
sys/dev/drm/i915/intel_hdmi.c
1205
tmp = I915_READ(intel_hdmi->hdmi_reg);
sys/dev/drm/i915/intel_hdmi.c
1266
temp = I915_READ(intel_hdmi->hdmi_reg);
sys/dev/drm/i915/intel_hdmi.c
1288
temp = I915_READ(intel_hdmi->hdmi_reg);
sys/dev/drm/i915/intel_hdmi.c
1340
temp = I915_READ(intel_hdmi->hdmi_reg);
sys/dev/drm/i915/intel_hdmi.c
1358
I915_READ(TRANS_CHICKEN1(pipe)) |
sys/dev/drm/i915/intel_hdmi.c
1376
I915_READ(TRANS_CHICKEN1(pipe)) &
sys/dev/drm/i915/intel_hdmi.c
1402
temp = I915_READ(intel_hdmi->hdmi_reg);
sys/dev/drm/i915/intel_hdmi.c
159
u32 val = I915_READ(VIDEO_DIP_CTL);
sys/dev/drm/i915/intel_hdmi.c
194
u32 val = I915_READ(VIDEO_DIP_CTL);
sys/dev/drm/i915/intel_hdmi.c
216
u32 val = I915_READ(reg);
sys/dev/drm/i915/intel_hdmi.c
2404
u32 temp = I915_READ(PEG_BAND_GAP_DATA);
sys/dev/drm/i915/intel_hdmi.c
253
u32 val = I915_READ(reg);
sys/dev/drm/i915/intel_hdmi.c
276
u32 val = I915_READ(reg);
sys/dev/drm/i915/intel_hdmi.c
314
u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
sys/dev/drm/i915/intel_hdmi.c
334
u32 val = I915_READ(reg);
sys/dev/drm/i915/intel_hdmi.c
370
u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
sys/dev/drm/i915/intel_hdmi.c
396
u32 val = I915_READ(ctl_reg);
sys/dev/drm/i915/intel_hdmi.c
422
u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
sys/dev/drm/i915/intel_hdmi.c
551
u32 val = I915_READ(reg);
sys/dev/drm/i915/intel_hdmi.c
58
WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
sys/dev/drm/i915/intel_hdmi.c
66
WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
sys/dev/drm/i915/intel_hdmi.c
702
u32 val = I915_READ(reg);
sys/dev/drm/i915/intel_hdmi.c
754
u32 val = I915_READ(reg);
sys/dev/drm/i915/intel_hdmi.c
798
u32 val = I915_READ(reg);
sys/dev/drm/i915/intel_hdmi.c
848
u32 val = I915_READ(reg);
sys/dev/drm/i915/intel_huc.c
123
status = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
sys/dev/drm/i915/intel_i2c.c
150
val = I915_READ(DSPCLK_GATE_D);
sys/dev/drm/i915/intel_i2c.c
163
val = I915_READ(SOUTH_DSPCLK_GATE_D);
sys/dev/drm/i915/intel_i2c.c
176
val = I915_READ(GEN9_CLKGATE_DIS_4);
sys/dev/drm/i915/intel_lpe_audio.c
343
audio_enable = I915_READ(VLV_AUD_PORT_EN_DBG(port));
sys/dev/drm/i915/intel_lrc.c
1803
if (I915_READ(RING_MI_MODE(engine->mmio_base)) & STOP_RING) {
sys/dev/drm/i915/intel_lvds.c
130
tmp = I915_READ(lvds_encoder->reg);
sys/dev/drm/i915/intel_lvds.c
148
tmp = I915_READ(PFIT_CONTROL);
sys/dev/drm/i915/intel_lvds.c
161
pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET;
sys/dev/drm/i915/intel_lvds.c
163
val = I915_READ(PP_ON_DELAYS(0));
sys/dev/drm/i915/intel_lvds.c
171
val = I915_READ(PP_OFF_DELAYS(0));
sys/dev/drm/i915/intel_lvds.c
177
val = I915_READ(PP_DIVISOR(0));
sys/dev/drm/i915/intel_lvds.c
215
val = I915_READ(PP_CONTROL(0));
sys/dev/drm/i915/intel_lvds.c
322
I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
sys/dev/drm/i915/intel_lvds.c
324
I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);
sys/dev/drm/i915/intel_lvds.c
340
I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON);
sys/dev/drm/i915/intel_lvds.c
344
I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
sys/dev/drm/i915/intel_lvds.c
819
val = I915_READ(lvds_encoder->reg);
sys/dev/drm/i915/intel_lvds.c
895
lvds = I915_READ(lvds_reg);
sys/dev/drm/i915/intel_lvds.c
92
val = I915_READ(lvds_reg);
sys/dev/drm/i915/intel_overlay.c
1252
attrs->gamma0 = I915_READ(OGAMC0);
sys/dev/drm/i915/intel_overlay.c
1253
attrs->gamma1 = I915_READ(OGAMC1);
sys/dev/drm/i915/intel_overlay.c
1254
attrs->gamma2 = I915_READ(OGAMC2);
sys/dev/drm/i915/intel_overlay.c
1255
attrs->gamma3 = I915_READ(OGAMC3);
sys/dev/drm/i915/intel_overlay.c
1256
attrs->gamma4 = I915_READ(OGAMC4);
sys/dev/drm/i915/intel_overlay.c
1257
attrs->gamma5 = I915_READ(OGAMC5);
sys/dev/drm/i915/intel_overlay.c
1434
error->dovsta = I915_READ(DOVSTA);
sys/dev/drm/i915/intel_overlay.c
1435
error->isr = I915_READ(ISR);
sys/dev/drm/i915/intel_overlay.c
315
tmp = I915_READ(DOVSTA);
sys/dev/drm/i915/intel_overlay.c
449
if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
sys/dev/drm/i915/intel_overlay.c
896
u32 pfit_control = I915_READ(PFIT_CONTROL);
sys/dev/drm/i915/intel_overlay.c
904
ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
sys/dev/drm/i915/intel_overlay.c
907
ratio = I915_READ(PFIT_AUTO_RATIOS);
sys/dev/drm/i915/intel_overlay.c
909
ratio = I915_READ(PFIT_PGM_RATIOS);
sys/dev/drm/i915/intel_panel.c
1012
val = I915_READ(UTIL_PIN_CTL);
sys/dev/drm/i915/intel_panel.c
1026
pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
sys/dev/drm/i915/intel_panel.c
1057
pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
sys/dev/drm/i915/intel_panel.c
1420
if ((I915_READ(CBR1_VLV) & CBR_PWM_CLOCK_MUX_SELECT) == 0) {
sys/dev/drm/i915/intel_panel.c
1500
alt = I915_READ(SOUTH_CHICKEN2) & LPT_PWM_GRANULARITY;
sys/dev/drm/i915/intel_panel.c
1502
alt = I915_READ(SOUTH_CHICKEN1) & SPT_PWM_GRANULARITY;
sys/dev/drm/i915/intel_panel.c
1505
pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
sys/dev/drm/i915/intel_panel.c
1508
pch_ctl2 = I915_READ(BLC_PWM_PCH_CTL2);
sys/dev/drm/i915/intel_panel.c
1535
pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
sys/dev/drm/i915/intel_panel.c
1538
pch_ctl2 = I915_READ(BLC_PWM_PCH_CTL2);
sys/dev/drm/i915/intel_panel.c
1554
cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2);
sys/dev/drm/i915/intel_panel.c
1567
ctl = I915_READ(BLC_PWM_CTL);
sys/dev/drm/i915/intel_panel.c
1606
ctl2 = I915_READ(BLC_PWM_CTL2);
sys/dev/drm/i915/intel_panel.c
1610
ctl = I915_READ(BLC_PWM_CTL);
sys/dev/drm/i915/intel_panel.c
1643
ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe));
sys/dev/drm/i915/intel_panel.c
1646
ctl = I915_READ(VLV_BLC_PWM_CTL(pipe));
sys/dev/drm/i915/intel_panel.c
1676
pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
sys/dev/drm/i915/intel_panel.c
1680
val = I915_READ(UTIL_PIN_CTL);
sys/dev/drm/i915/intel_panel.c
1687
I915_READ(BXT_BLC_PWM_FREQ(panel->backlight.controller));
sys/dev/drm/i915/intel_panel.c
1721
pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
sys/dev/drm/i915/intel_panel.c
1725
I915_READ(BXT_BLC_PWM_FREQ(panel->backlight.controller));
sys/dev/drm/i915/intel_panel.c
467
return I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK;
sys/dev/drm/i915/intel_panel.c
474
return I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
sys/dev/drm/i915/intel_panel.c
483
val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
sys/dev/drm/i915/intel_panel.c
502
return I915_READ(VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK;
sys/dev/drm/i915/intel_panel.c
518
return I915_READ(BXT_BLC_PWM_DUTY(panel->backlight.controller));
sys/dev/drm/i915/intel_panel.c
535
u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK;
sys/dev/drm/i915/intel_panel.c
545
tmp = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
sys/dev/drm/i915/intel_panel.c
573
tmp = I915_READ(BLC_PWM_CTL) & ~mask;
sys/dev/drm/i915/intel_panel.c
584
tmp = I915_READ(VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK;
sys/dev/drm/i915/intel_panel.c
672
tmp = I915_READ(BLC_PWM_CPU_CTL2);
sys/dev/drm/i915/intel_panel.c
678
tmp = I915_READ(BLC_PWM_PCH_CTL1);
sys/dev/drm/i915/intel_panel.c
690
tmp = I915_READ(BLC_PWM_CPU_CTL2);
sys/dev/drm/i915/intel_panel.c
693
tmp = I915_READ(BLC_PWM_PCH_CTL1);
sys/dev/drm/i915/intel_panel.c
709
tmp = I915_READ(BLC_PWM_CTL2);
sys/dev/drm/i915/intel_panel.c
722
tmp = I915_READ(VLV_BLC_PWM_CTL2(pipe));
sys/dev/drm/i915/intel_panel.c
735
tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
sys/dev/drm/i915/intel_panel.c
740
val = I915_READ(UTIL_PIN_CTL);
sys/dev/drm/i915/intel_panel.c
755
tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
sys/dev/drm/i915/intel_panel.c
809
pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
sys/dev/drm/i915/intel_panel.c
817
schicken = I915_READ(SOUTH_CHICKEN2);
sys/dev/drm/i915/intel_panel.c
824
schicken = I915_READ(SOUTH_CHICKEN1);
sys/dev/drm/i915/intel_panel.c
860
cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2);
sys/dev/drm/i915/intel_panel.c
867
pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
sys/dev/drm/i915/intel_panel.c
905
ctl = I915_READ(BLC_PWM_CTL);
sys/dev/drm/i915/intel_panel.c
945
ctl2 = I915_READ(BLC_PWM_CTL2);
sys/dev/drm/i915/intel_panel.c
980
ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe));
sys/dev/drm/i915/intel_pm.c
100
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
sys/dev/drm/i915/intel_pm.c
107
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
sys/dev/drm/i915/intel_pm.c
114
I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
sys/dev/drm/i915/intel_pm.c
127
I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
sys/dev/drm/i915/intel_pm.c
132
u32 val = I915_READ(CHICKEN_MISC_2);
sys/dev/drm/i915/intel_pm.c
145
tmp = I915_READ(CLKCFG);
sys/dev/drm/i915/intel_pm.c
175
tmp = I915_READ(CSHRDDR3CTL);
sys/dev/drm/i915/intel_pm.c
2421
fwater_lo = I915_READ(FW_BLC) & ~0xfff;
sys/dev/drm/i915/intel_pm.c
2905
uint32_t sskpd = I915_READ(MCH_SSKPD);
sys/dev/drm/i915/intel_pm.c
2912
uint32_t mltr = I915_READ(MLTR_ILK);
sys/dev/drm/i915/intel_pm.c
355
was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
sys/dev/drm/i915/intel_pm.c
3564
val = I915_READ(WM_MISC);
sys/dev/drm/i915/intel_pm.c
3571
val = I915_READ(DISP_ARB_CTL2);
sys/dev/drm/i915/intel_pm.c
3581
val = I915_READ(DISP_ARB_CTL);
sys/dev/drm/i915/intel_pm.c
359
was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
sys/dev/drm/i915/intel_pm.c
3628
if (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
sys/dev/drm/i915/intel_pm.c
363
val = I915_READ(DSPFW3);
sys/dev/drm/i915/intel_pm.c
372
was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
sys/dev/drm/i915/intel_pm.c
383
was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
sys/dev/drm/i915/intel_pm.c
3966
val = I915_READ(CUR_BUF_CFG(pipe));
sys/dev/drm/i915/intel_pm.c
3972
val = I915_READ(PLANE_CTL(pipe, plane_id));
sys/dev/drm/i915/intel_pm.c
3983
val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
sys/dev/drm/i915/intel_pm.c
3989
val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
sys/dev/drm/i915/intel_pm.c
483
dsparb = I915_READ(DSPARB);
sys/dev/drm/i915/intel_pm.c
484
dsparb2 = I915_READ(DSPARB2);
sys/dev/drm/i915/intel_pm.c
489
dsparb = I915_READ(DSPARB);
sys/dev/drm/i915/intel_pm.c
490
dsparb2 = I915_READ(DSPARB2);
sys/dev/drm/i915/intel_pm.c
495
dsparb2 = I915_READ(DSPARB2);
sys/dev/drm/i915/intel_pm.c
496
dsparb3 = I915_READ(DSPARB3);
sys/dev/drm/i915/intel_pm.c
514
uint32_t dsparb = I915_READ(DSPARB);
sys/dev/drm/i915/intel_pm.c
530
uint32_t dsparb = I915_READ(DSPARB);
sys/dev/drm/i915/intel_pm.c
547
uint32_t dsparb = I915_READ(DSPARB);
sys/dev/drm/i915/intel_pm.c
5562
val = I915_READ(PLANE_WM(pipe, plane_id, level));
sys/dev/drm/i915/intel_pm.c
5564
val = I915_READ(CUR_WM(pipe, level));
sys/dev/drm/i915/intel_pm.c
5570
val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
sys/dev/drm/i915/intel_pm.c
5572
val = I915_READ(CUR_WM_TRANS(pipe));
sys/dev/drm/i915/intel_pm.c
5580
out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
sys/dev/drm/i915/intel_pm.c
5631
hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
sys/dev/drm/i915/intel_pm.c
5633
hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
sys/dev/drm/i915/intel_pm.c
5678
tmp = I915_READ(DSPFW1);
sys/dev/drm/i915/intel_pm.c
5684
tmp = I915_READ(DSPFW2);
sys/dev/drm/i915/intel_pm.c
5692
tmp = I915_READ(DSPFW3);
sys/dev/drm/i915/intel_pm.c
5706
tmp = I915_READ(VLV_DDL(pipe));
sys/dev/drm/i915/intel_pm.c
5718
tmp = I915_READ(DSPFW1);
sys/dev/drm/i915/intel_pm.c
5724
tmp = I915_READ(DSPFW2);
sys/dev/drm/i915/intel_pm.c
5729
tmp = I915_READ(DSPFW3);
sys/dev/drm/i915/intel_pm.c
5733
tmp = I915_READ(DSPFW7_CHV);
sys/dev/drm/i915/intel_pm.c
5737
tmp = I915_READ(DSPFW8_CHV);
sys/dev/drm/i915/intel_pm.c
5741
tmp = I915_READ(DSPFW9_CHV);
sys/dev/drm/i915/intel_pm.c
5745
tmp = I915_READ(DSPHOWM);
sys/dev/drm/i915/intel_pm.c
5757
tmp = I915_READ(DSPFW7);
sys/dev/drm/i915/intel_pm.c
5761
tmp = I915_READ(DSPHOWM);
sys/dev/drm/i915/intel_pm.c
5783
wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
sys/dev/drm/i915/intel_pm.c
5925
wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
sys/dev/drm/i915/intel_pm.c
6069
I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
sys/dev/drm/i915/intel_pm.c
6070
I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
sys/dev/drm/i915/intel_pm.c
6071
I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
sys/dev/drm/i915/intel_pm.c
6090
hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
sys/dev/drm/i915/intel_pm.c
6091
hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
sys/dev/drm/i915/intel_pm.c
6092
hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
sys/dev/drm/i915/intel_pm.c
6094
hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
sys/dev/drm/i915/intel_pm.c
6096
hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
sys/dev/drm/i915/intel_pm.c
6097
hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
sys/dev/drm/i915/intel_pm.c
6101
hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
sys/dev/drm/i915/intel_pm.c
6104
hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
sys/dev/drm/i915/intel_pm.c
6108
!(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
sys/dev/drm/i915/intel_pm.c
6165
val = I915_READ(DISP_ARB_CTL2);
sys/dev/drm/i915/intel_pm.c
6224
rgvmodectl = I915_READ(MEMMODECTL);
sys/dev/drm/i915/intel_pm.c
6227
I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
sys/dev/drm/i915/intel_pm.c
6228
I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
sys/dev/drm/i915/intel_pm.c
6246
vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
sys/dev/drm/i915/intel_pm.c
6271
if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
sys/dev/drm/i915/intel_pm.c
6277
dev_priv->ips.last_count1 = I915_READ(DMIEC) +
sys/dev/drm/i915/intel_pm.c
6278
I915_READ(DDREC) + I915_READ(CSIEC);
sys/dev/drm/i915/intel_pm.c
6280
dev_priv->ips.last_count2 = I915_READ(GFXEC);
sys/dev/drm/i915/intel_pm.c
6295
I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
sys/dev/drm/i915/intel_pm.c
6297
I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
sys/dev/drm/i915/intel_pm.c
6299
I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
sys/dev/drm/i915/intel_pm.c
66
I915_READ(CHICKEN_PAR1_1) |
sys/dev/drm/i915/intel_pm.c
6753
rc_ctl = I915_READ(GEN6_RC_CONTROL);
sys/dev/drm/i915/intel_pm.c
6754
rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
sys/dev/drm/i915/intel_pm.c
6762
if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
sys/dev/drm/i915/intel_pm.c
6771
rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
sys/dev/drm/i915/intel_pm.c
6778
if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
sys/dev/drm/i915/intel_pm.c
6779
((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
sys/dev/drm/i915/intel_pm.c
6780
((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
sys/dev/drm/i915/intel_pm.c
6781
((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
sys/dev/drm/i915/intel_pm.c
6786
if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
sys/dev/drm/i915/intel_pm.c
6787
!I915_READ(GEN8_PUSHBUS_ENABLE) ||
sys/dev/drm/i915/intel_pm.c
6788
!I915_READ(GEN8_PUSHBUS_SHIFT)) {
sys/dev/drm/i915/intel_pm.c
6793
if (!I915_READ(GEN6_GFXPAUSE)) {
sys/dev/drm/i915/intel_pm.c
6798
if (!I915_READ(GEN8_MISC_CTRL0)) {
sys/dev/drm/i915/intel_pm.c
6840
u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
sys/dev/drm/i915/intel_pm.c
6845
u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
sys/dev/drm/i915/intel_pm.c
7094
gtfifodbg = I915_READ(GTFIFODBG);
sys/dev/drm/i915/intel_pm.c
72
I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
sys/dev/drm/i915/intel_pm.c
7206
min_ring_freq = I915_READ(DCLK) & 0xf;
sys/dev/drm/i915/intel_pm.c
7376
unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
sys/dev/drm/i915/intel_pm.c
7386
unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
sys/dev/drm/i915/intel_pm.c
7397
pcbr = I915_READ(VLV_PCBR);
sys/dev/drm/i915/intel_pm.c
7407
DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
sys/dev/drm/i915/intel_pm.c
7417
pcbr = I915_READ(VLV_PCBR);
sys/dev/drm/i915/intel_pm.c
7454
DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
sys/dev/drm/i915/intel_pm.c
7584
gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
sys/dev/drm/i915/intel_pm.c
76
I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
sys/dev/drm/i915/intel_pm.c
7620
pcbr = I915_READ(VLV_PCBR);
sys/dev/drm/i915/intel_pm.c
7681
gtfifodbg = I915_READ(GTFIFODBG);
sys/dev/drm/i915/intel_pm.c
7805
count1 = I915_READ(DMIEC);
sys/dev/drm/i915/intel_pm.c
7806
count2 = I915_READ(DDREC);
sys/dev/drm/i915/intel_pm.c
7807
count3 = I915_READ(CSIEC);
sys/dev/drm/i915/intel_pm.c
7861
tsfs = I915_READ(TSFS);
sys/dev/drm/i915/intel_pm.c
7908
count = I915_READ(GFXEC);
sys/dev/drm/i915/intel_pm.c
7945
pxvid = I915_READ(PXVFREQ(dev_priv->gt_pm.rps.cur_freq));
sys/dev/drm/i915/intel_pm.c
80
I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
sys/dev/drm/i915/intel_pm.c
8185
u32 pxvidfreq = I915_READ(PXVFREQ(i));
sys/dev/drm/i915/intel_pm.c
8227
lcfuse = I915_READ(LCFUSE02);
sys/dev/drm/i915/intel_pm.c
8492
I915_READ(DSPCNTR(pipe)) |
sys/dev/drm/i915/intel_pm.c
8495
I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
sys/dev/drm/i915/intel_pm.c
85
I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
sys/dev/drm/i915/intel_pm.c
8526
(I915_READ(ILK_DISPLAY_CHICKEN2) |
sys/dev/drm/i915/intel_pm.c
8530
(I915_READ(DISP_ARB_CTL) |
sys/dev/drm/i915/intel_pm.c
8543
I915_READ(ILK_DISPLAY_CHICKEN1) |
sys/dev/drm/i915/intel_pm.c
8546
I915_READ(ILK_DISPLAY_CHICKEN2) |
sys/dev/drm/i915/intel_pm.c
8553
I915_READ(ILK_DISPLAY_CHICKEN2) |
sys/dev/drm/i915/intel_pm.c
8584
I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
sys/dev/drm/i915/intel_pm.c
8590
val = I915_READ(TRANS_CHICKEN2(pipe));
sys/dev/drm/i915/intel_pm.c
8611
tmp = I915_READ(MCH_SSKPD);
sys/dev/drm/i915/intel_pm.c
8624
I915_READ(ILK_DISPLAY_CHICKEN2) |
sys/dev/drm/i915/intel_pm.c
8649
I915_READ(GEN6_UCGCTL1) |
sys/dev/drm/i915/intel_pm.c
8694
I915_READ(ILK_DISPLAY_CHICKEN1) |
sys/dev/drm/i915/intel_pm.c
8697
I915_READ(ILK_DISPLAY_CHICKEN2) |
sys/dev/drm/i915/intel_pm.c
8700
I915_READ(ILK_DSPCLK_GATE_D) |
sys/dev/drm/i915/intel_pm.c
871
reg = I915_READ(DSPFW1);
sys/dev/drm/i915/intel_pm.c
8713
uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
sys/dev/drm/i915/intel_pm.c
8737
I915_READ(SOUTH_DSPCLK_GATE_D) |
sys/dev/drm/i915/intel_pm.c
8742
I915_READ(TRANS_CHICKEN1(PIPE_A)) |
sys/dev/drm/i915/intel_pm.c
8749
uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
sys/dev/drm/i915/intel_pm.c
8764
misccpctl = I915_READ(GEN7_MISCCPCTL);
sys/dev/drm/i915/intel_pm.c
8767
val = I915_READ(GEN8_L3SQCREG1);
sys/dev/drm/i915/intel_pm.c
8786
I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);
sys/dev/drm/i915/intel_pm.c
8795
I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
sys/dev/drm/i915/intel_pm.c
881
reg = I915_READ(DSPFW3);
sys/dev/drm/i915/intel_pm.c
8810
I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
sys/dev/drm/i915/intel_pm.c
8813
I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
sys/dev/drm/i915/intel_pm.c
8816
val = I915_READ(SLICE_UNIT_LEVEL_CLKGATE);
sys/dev/drm/i915/intel_pm.c
8825
val = I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE);
sys/dev/drm/i915/intel_pm.c
8831
val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE);
sys/dev/drm/i915/intel_pm.c
8842
I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
sys/dev/drm/i915/intel_pm.c
8852
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
sys/dev/drm/i915/intel_pm.c
8857
I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
sys/dev/drm/i915/intel_pm.c
8861
I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
sys/dev/drm/i915/intel_pm.c
8870
I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
sys/dev/drm/i915/intel_pm.c
8874
I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
sys/dev/drm/i915/intel_pm.c
8886
I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
sys/dev/drm/i915/intel_pm.c
8890
I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
sys/dev/drm/i915/intel_pm.c
8895
I915_READ(CHICKEN_PIPESL_1(pipe)) |
sys/dev/drm/i915/intel_pm.c
890
reg = I915_READ(DSPFW3);
sys/dev/drm/i915/intel_pm.c
8902
I915_READ(GEN7_FF_THREAD_MODE) &
sys/dev/drm/i915/intel_pm.c
8909
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
sys/dev/drm/i915/intel_pm.c
8919
I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
sys/dev/drm/i915/intel_pm.c
8930
I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
sys/dev/drm/i915/intel_pm.c
8942
I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
sys/dev/drm/i915/intel_pm.c
8947
I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
sys/dev/drm/i915/intel_pm.c
8976
I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
sys/dev/drm/i915/intel_pm.c
899
reg = I915_READ(DSPFW3);
sys/dev/drm/i915/intel_pm.c
90
I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
sys/dev/drm/i915/intel_pm.c
9025
I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
sys/dev/drm/i915/intel_pm.c
9037
I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
sys/dev/drm/i915/intel_pm.c
9065
snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
sys/dev/drm/i915/intel_pm.c
9097
I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
sys/dev/drm/i915/intel_pm.c
9106
I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
sys/dev/drm/i915/intel_pm.c
9122
I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
sys/dev/drm/i915/intel_pm.c
9161
I915_READ(GEN7_FF_THREAD_MODE) &
sys/dev/drm/i915/intel_pm.c
9169
I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
sys/dev/drm/i915/intel_pm.c
9173
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
sys/dev/drm/i915/intel_pm.c
9247
u32 dstate = I915_READ(D_STATE);
sys/dev/drm/i915/intel_psr.c
175
u32 val = I915_READ(PSR_EVENT(cpu_transcoder));
sys/dev/drm/i915/intel_psr.c
406
val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK;
sys/dev/drm/i915/intel_psr.c
507
I915_READ(HSW_STEREO_3D_CTL(crtc_state->cpu_transcoder)) &
sys/dev/drm/i915/intel_psr.c
542
WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
sys/dev/drm/i915/intel_psr.c
543
WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
sys/dev/drm/i915/intel_psr.c
569
u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder));
sys/dev/drm/i915/intel_psr.c
673
I915_READ(EDP_PSR2_CTL) &
sys/dev/drm/i915/intel_psr.c
681
I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
sys/dev/drm/i915/intel_psr.c
693
WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
sys/dev/drm/i915/intel_psr.c
695
WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
sys/dev/drm/i915/intel_psr.c
936
val = I915_READ(EDP_PSR2_CTL);
sys/dev/drm/i915/intel_psr.c
940
val = I915_READ(EDP_PSR_CTL);
sys/dev/drm/i915/intel_ringbuffer.h
38
#define I915_READ_TAIL(engine) I915_READ(RING_TAIL((engine)->mmio_base))
sys/dev/drm/i915/intel_ringbuffer.h
41
#define I915_READ_START(engine) I915_READ(RING_START((engine)->mmio_base))
sys/dev/drm/i915/intel_ringbuffer.h
44
#define I915_READ_HEAD(engine) I915_READ(RING_HEAD((engine)->mmio_base))
sys/dev/drm/i915/intel_ringbuffer.h
47
#define I915_READ_CTL(engine) I915_READ(RING_CTL((engine)->mmio_base))
sys/dev/drm/i915/intel_ringbuffer.h
50
#define I915_READ_IMR(engine) I915_READ(RING_IMR((engine)->mmio_base))
sys/dev/drm/i915/intel_ringbuffer.h
53
#define I915_READ_MODE(engine) I915_READ(RING_MI_MODE((engine)->mmio_base))
sys/dev/drm/i915/intel_runtime_pm.c
1084
I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
sys/dev/drm/i915/intel_runtime_pm.c
1096
I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
sys/dev/drm/i915/intel_runtime_pm.c
1158
(I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
sys/dev/drm/i915/intel_runtime_pm.c
1207
I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask,
sys/dev/drm/i915/intel_runtime_pm.c
3144
val = I915_READ(reg);
sys/dev/drm/i915/intel_runtime_pm.c
3150
status = I915_READ(reg) & DBUF_POWER_STATE;
sys/dev/drm/i915/intel_runtime_pm.c
316
ret = I915_READ(regs->bios) & req_mask ? 1 : 0;
sys/dev/drm/i915/intel_runtime_pm.c
317
ret |= I915_READ(regs->driver) & req_mask ? 2 : 0;
sys/dev/drm/i915/intel_runtime_pm.c
319
ret |= I915_READ(regs->kvmr) & req_mask ? 4 : 0;
sys/dev/drm/i915/intel_runtime_pm.c
320
ret |= I915_READ(regs->debug) & req_mask ? 8 : 0;
sys/dev/drm/i915/intel_runtime_pm.c
3201
I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST);
sys/dev/drm/i915/intel_runtime_pm.c
3202
I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) | DBUF_POWER_REQUEST);
sys/dev/drm/i915/intel_runtime_pm.c
3207
if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
sys/dev/drm/i915/intel_runtime_pm.c
3208
!(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
sys/dev/drm/i915/intel_runtime_pm.c
3216
I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) & ~DBUF_POWER_REQUEST);
sys/dev/drm/i915/intel_runtime_pm.c
3217
I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) & ~DBUF_POWER_REQUEST);
sys/dev/drm/i915/intel_runtime_pm.c
3222
if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
sys/dev/drm/i915/intel_runtime_pm.c
3223
(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
sys/dev/drm/i915/intel_runtime_pm.c
3251
val = I915_READ(HSW_NDE_RSTWRN_OPT);
sys/dev/drm/i915/intel_runtime_pm.c
3318
val = I915_READ(HSW_NDE_RSTWRN_OPT);
sys/dev/drm/i915/intel_runtime_pm.c
3401
val = I915_READ(ICL_PORT_COMP_DW3(port));
sys/dev/drm/i915/intel_runtime_pm.c
342
wait_for((disabled = !(I915_READ(regs->driver) &
sys/dev/drm/i915/intel_runtime_pm.c
3423
val = I915_READ(ICL_PORT_COMP_DW1(port));
sys/dev/drm/i915/intel_runtime_pm.c
3441
val = I915_READ(HSW_NDE_RSTWRN_OPT);
sys/dev/drm/i915/intel_runtime_pm.c
3446
val = I915_READ(CHICKEN_MISC_2);
sys/dev/drm/i915/intel_runtime_pm.c
3453
val = I915_READ(CNL_PORT_COMP_DW0);
sys/dev/drm/i915/intel_runtime_pm.c
3458
val = I915_READ(CNL_PORT_CL1CM_DW5);
sys/dev/drm/i915/intel_runtime_pm.c
3510
val = I915_READ(CHICKEN_MISC_2);
sys/dev/drm/i915/intel_runtime_pm.c
3526
val = I915_READ(HSW_NDE_RSTWRN_OPT);
sys/dev/drm/i915/intel_runtime_pm.c
3532
val = I915_READ(ICL_PHY_MISC(port));
sys/dev/drm/i915/intel_runtime_pm.c
3538
val = I915_READ(ICL_PORT_COMP_DW0(port));
sys/dev/drm/i915/intel_runtime_pm.c
3543
val = I915_READ(ICL_PORT_CL_DW5(port));
sys/dev/drm/i915/intel_runtime_pm.c
3599
val = I915_READ(ICL_PHY_MISC(port));
sys/dev/drm/i915/intel_runtime_pm.c
3634
uint32_t status = I915_READ(DPLL(PIPE_A));
sys/dev/drm/i915/intel_runtime_pm.c
3665
uint32_t status = I915_READ(DPIO_PHY_STATUS);
sys/dev/drm/i915/intel_runtime_pm.c
3702
I915_READ(DPIO_CTL) & DPIO_CMNRST)
sys/dev/drm/i915/intel_runtime_pm.c
385
val = I915_READ(regs->driver);
sys/dev/drm/i915/intel_runtime_pm.c
393
val = I915_READ(CNL_AUX_ANAOVRD1(pw_idx));
sys/dev/drm/i915/intel_runtime_pm.c
416
val = I915_READ(regs->driver);
sys/dev/drm/i915/intel_runtime_pm.c
432
val = I915_READ(regs->driver);
sys/dev/drm/i915/intel_runtime_pm.c
435
val = I915_READ(ICL_PORT_CL_DW12(port));
sys/dev/drm/i915/intel_runtime_pm.c
450
val = I915_READ(ICL_PORT_CL_DW12(port));
sys/dev/drm/i915/intel_runtime_pm.c
453
val = I915_READ(regs->driver);
sys/dev/drm/i915/intel_runtime_pm.c
472
return (I915_READ(regs->driver) & mask) == mask;
sys/dev/drm/i915/intel_runtime_pm.c
477
WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
sys/dev/drm/i915/intel_runtime_pm.c
479
WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
sys/dev/drm/i915/intel_runtime_pm.c
481
WARN_ONCE(I915_READ(HSW_PWR_WELL_CTL2) &
sys/dev/drm/i915/intel_runtime_pm.c
500
WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
sys/dev/drm/i915/intel_runtime_pm.c
527
v = I915_READ(DC_STATE_EN);
sys/dev/drm/i915/intel_runtime_pm.c
566
val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv);
sys/dev/drm/i915/intel_runtime_pm.c
604
val = I915_READ(DC_STATE_EN);
sys/dev/drm/i915/intel_runtime_pm.c
645
WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
sys/dev/drm/i915/intel_runtime_pm.c
647
WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
sys/dev/drm/i915/intel_runtime_pm.c
648
WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
sys/dev/drm/i915/intel_runtime_pm.c
679
WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
sys/dev/drm/i915/intel_runtime_pm.c
694
I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
sys/dev/drm/i915/intel_runtime_pm.c
702
WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
sys/dev/drm/i915/intel_runtime_pm.c
704
WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
sys/dev/drm/i915/intel_runtime_pm.c
718
I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
sys/dev/drm/i915/intel_runtime_pm.c
730
u32 bios_req = I915_READ(regs->bios);
sys/dev/drm/i915/intel_runtime_pm.c
734
u32 drv_req = I915_READ(regs->driver);
sys/dev/drm/i915/intel_runtime_pm.c
784
return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
sys/dev/drm/i915/intel_runtime_pm.c
789
u32 tmp = I915_READ(DBUF_CTL);
sys/dev/drm/i915/intel_runtime_pm.c
844
if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0)
sys/dev/drm/i915/intel_runtime_pm.c
846
if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0)
sys/dev/drm/i915/intel_runtime_pm.c
860
return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE &&
sys/dev/drm/i915/intel_runtime_pm.c
861
I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
sys/dev/drm/i915/intel_runtime_pm.c
967
val = I915_READ(DSPCLK_GATE_D);
sys/dev/drm/i915/intel_runtime_pm.c
998
u32 val = I915_READ(DPLL(pipe));
sys/dev/drm/i915/intel_sdvo.c
1358
sdvox = I915_READ(intel_sdvo->sdvo_reg);
sys/dev/drm/i915/intel_sdvo.c
1409
val = I915_READ(sdvo_reg);
sys/dev/drm/i915/intel_sdvo.c
1452
sdvox = I915_READ(intel_sdvo->sdvo_reg);
sys/dev/drm/i915/intel_sdvo.c
1543
temp = I915_READ(intel_sdvo->sdvo_reg);
sys/dev/drm/i915/intel_sdvo.c
1600
temp = I915_READ(intel_sdvo->sdvo_reg);
sys/dev/drm/i915/intel_sdvo.c
230
cval = I915_READ(GEN3_SDVOC);
sys/dev/drm/i915/intel_sdvo.c
232
bval = I915_READ(GEN3_SDVOB);
sys/dev/drm/i915/intel_sideband.c
236
if (I915_READ(SBI_CTL_STAT) & SBI_RESPONSE_FAIL) {
sys/dev/drm/i915/intel_sideband.c
241
return I915_READ(SBI_DATA);
sys/dev/drm/i915/intel_sideband.c
276
if (I915_READ(SBI_CTL_STAT) & SBI_RESPONSE_FAIL) {
sys/dev/drm/i915/intel_sideband.c
75
*val = I915_READ(VLV_IOSF_DATA);
sys/dev/drm/i915/intel_sprite.c
1048
ret = I915_READ(DVSCNTR(plane->pipe)) & DVS_ENABLE;
sys/dev/drm/i915/intel_sprite.c
451
ret = I915_READ(PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;
sys/dev/drm/i915/intel_sprite.c
715
ret = I915_READ(SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;
sys/dev/drm/i915/intel_sprite.c
882
ret = I915_READ(SPRCTL(plane->pipe)) & SPRITE_ENABLE;
sys/dev/drm/i915/intel_tv.c
1002
tv_ctl = I915_READ(TV_CTL);
sys/dev/drm/i915/intel_tv.c
1109
I915_WRITE(TV_DAC, I915_READ(TV_DAC) & TV_DAC_SAVE);
sys/dev/drm/i915/intel_tv.c
1151
save_tv_dac = tv_dac = I915_READ(TV_DAC);
sys/dev/drm/i915/intel_tv.c
1152
save_tv_ctl = tv_ctl = I915_READ(TV_CTL);
sys/dev/drm/i915/intel_tv.c
1185
tv_dac = I915_READ(TV_DAC);
sys/dev/drm/i915/intel_tv.c
1445
if ((I915_READ(TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
sys/dev/drm/i915/intel_tv.c
1457
save_tv_dac = I915_READ(TV_DAC);
sys/dev/drm/i915/intel_tv.c
1460
tv_dac_on = I915_READ(TV_DAC);
sys/dev/drm/i915/intel_tv.c
1463
tv_dac_off = I915_READ(TV_DAC);
sys/dev/drm/i915/intel_tv.c
802
u32 tmp = I915_READ(TV_CTL);
sys/dev/drm/i915/intel_tv.c
821
I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE);
sys/dev/drm/i915/intel_tv.c
832
I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE);
sys/dev/drm/i915/intel_uc.c
45
guc_status = I915_READ(GUC_STATUS);
sys/dev/drm/i915/intel_uncore.c
1705
reg->val = I915_READ(entry->offset_ldw);
sys/dev/drm/i915/intel_uncore.c
1810
I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
sys/dev/drm/i915/intel_uncore.c
1833
I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
sys/dev/drm/i915/intel_wopcm.c
229
reg_val = I915_READ(reg);
sys/dev/drm/i915/intel_wopcm.c
277
I915_READ(DMA_GUC_WOPCM_OFFSET));
sys/dev/drm/i915/intel_wopcm.c
278
DRM_ERROR("GUC_WOPCM_SIZE=%#x\n", I915_READ(GUC_WOPCM_SIZE));
sys/dev/drm/i915/intel_workarounds.c
788
u32 fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
sys/dev/drm/i915/vlv_dsi.c
1044
bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
sys/dev/drm/i915/vlv_dsi.c
1053
enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
sys/dev/drm/i915/vlv_dsi.c
1057
u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port));
sys/dev/drm/i915/vlv_dsi.c
1064
if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
sys/dev/drm/i915/vlv_dsi.c
1068
u32 tmp = I915_READ(MIPI_CTRL(port));
sys/dev/drm/i915/vlv_dsi.c
111
u32 val = I915_READ(reg);
sys/dev/drm/i915/vlv_dsi.c
1116
if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
sys/dev/drm/i915/vlv_dsi.c
1120
fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
sys/dev/drm/i915/vlv_dsi.c
1132
I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
sys/dev/drm/i915/vlv_dsi.c
1134
I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
sys/dev/drm/i915/vlv_dsi.c
1136
I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
sys/dev/drm/i915/vlv_dsi.c
1139
hfp = I915_READ(MIPI_HFP_COUNT(port));
sys/dev/drm/i915/vlv_dsi.c
1145
hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port));
sys/dev/drm/i915/vlv_dsi.c
1146
hbp = I915_READ(MIPI_HBP_COUNT(port));
sys/dev/drm/i915/vlv_dsi.c
1163
vfp = I915_READ(MIPI_VFP_COUNT(port));
sys/dev/drm/i915/vlv_dsi.c
1164
vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
sys/dev/drm/i915/vlv_dsi.c
1165
vbp = I915_READ(MIPI_VBP_COUNT(port));
sys/dev/drm/i915/vlv_dsi.c
1430
tmp = I915_READ(MIPI_CTRL(PORT_A));
sys/dev/drm/i915/vlv_dsi.c
1436
tmp = I915_READ(MIPI_CTRL(port));
sys/dev/drm/i915/vlv_dsi.c
1443
tmp = I915_READ(MIPI_CTRL(port));
sys/dev/drm/i915/vlv_dsi.c
1614
val = I915_READ(MIPI_DSI_FUNC_PRG(port));
sys/dev/drm/i915/vlv_dsi.c
1700
val = I915_READ(DSPCNTR(i9xx_plane));
sys/dev/drm/i915/vlv_dsi.c
265
if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
sys/dev/drm/i915/vlv_dsi.c
373
tmp = I915_READ(MIPI_CTRL(port));
sys/dev/drm/i915/vlv_dsi.c
378
tmp = I915_READ(MIPI_CTRL(PORT_A));
sys/dev/drm/i915/vlv_dsi.c
384
tmp = I915_READ(MIPI_CTRL(port));
sys/dev/drm/i915/vlv_dsi.c
385
if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
sys/dev/drm/i915/vlv_dsi.c
402
cold_boot |= !(I915_READ(MIPI_DEVICE_READY(port)) &
sys/dev/drm/i915/vlv_dsi.c
425
val = I915_READ(MIPI_CTRL(PORT_A));
sys/dev/drm/i915/vlv_dsi.c
430
if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
sys/dev/drm/i915/vlv_dsi.c
431
val = I915_READ(MIPI_DEVICE_READY(port));
sys/dev/drm/i915/vlv_dsi.c
438
val = I915_READ(MIPI_DEVICE_READY(port));
sys/dev/drm/i915/vlv_dsi.c
449
val = I915_READ(MIPI_DEVICE_READY(port));
sys/dev/drm/i915/vlv_dsi.c
455
val = I915_READ(MIPI_DEVICE_READY(port));
sys/dev/drm/i915/vlv_dsi.c
460
val = I915_READ(MIPI_CTRL(port));
sys/dev/drm/i915/vlv_dsi.c
494
val = I915_READ(BXT_MIPI_PORT_CTRL(port));
sys/dev/drm/i915/vlv_dsi.c
501
val = I915_READ(MIPI_DEVICE_READY(port));
sys/dev/drm/i915/vlv_dsi.c
537
val = I915_READ(MIPI_PORT_CTRL(PORT_A));
sys/dev/drm/i915/vlv_dsi.c
570
val = I915_READ(MIPI_DEVICE_READY(port));
sys/dev/drm/i915/vlv_dsi.c
601
tmp = I915_READ(MIPI_CTRL(PORT_A));
sys/dev/drm/i915/vlv_dsi.c
615
tmp = I915_READ(MIPI_CTRL(port));
sys/dev/drm/i915/vlv_dsi.c
663
val = I915_READ(port_ctrl);
sys/dev/drm/i915/vlv_dsi.c
684
temp = I915_READ(MIPI_CTRL(port));
sys/dev/drm/i915/vlv_dsi.c
691
temp = I915_READ(VLV_CHICKEN_3);
sys/dev/drm/i915/vlv_dsi.c
704
temp = I915_READ(port_ctrl);
sys/dev/drm/i915/vlv_dsi.c
738
temp = I915_READ(port_ctrl);
sys/dev/drm/i915/vlv_dsi.c
827
val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
sys/dev/drm/i915/vlv_dsi.c
840
val = I915_READ(DSPCLK_GATE_D);
sys/dev/drm/i915/vlv_dsi.c
985
val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
sys/dev/drm/i915/vlv_dsi.c
997
val = I915_READ(DSPCLK_GATE_D);
sys/dev/drm/i915/vlv_dsi_pll.c
202
val = I915_READ(BXT_DSI_PLL_ENABLE);
sys/dev/drm/i915/vlv_dsi_pll.c
216
val = I915_READ(BXT_DSI_PLL_CTL);
sys/dev/drm/i915/vlv_dsi_pll.c
239
val = I915_READ(BXT_DSI_PLL_ENABLE);
sys/dev/drm/i915/vlv_dsi_pll.c
345
config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL);
sys/dev/drm/i915/vlv_dsi_pll.c
366
temp = I915_READ(MIPI_CTRL(port));
sys/dev/drm/i915/vlv_dsi_pll.c
435
tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
sys/dev/drm/i915/vlv_dsi_pll.c
545
val = I915_READ(BXT_DSI_PLL_ENABLE);
sys/dev/drm/i915/vlv_dsi_pll.c
570
tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
sys/dev/drm/i915/vlv_dsi_pll.c
577
tmp = I915_READ(MIPIO_TXESC_CLK_DIV1);
sys/dev/drm/i915/vlv_dsi_pll.c
581
tmp = I915_READ(MIPIO_TXESC_CLK_DIV2);
