I915_NUM_ENGINES
struct intel_vgpu_execlist execlist[I915_NUM_ENGINES];
struct list_head workload_q_head[I915_NUM_ENGINES];
DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES);
struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES];
struct intel_engine_cs *engine[I915_NUM_ENGINES];
(id__) < I915_NUM_ENGINES; \
BUILD_BUG_ON(I915_NUM_ENGINES > 16);
} __engine[I915_NUM_ENGINES];
for (i = 0; i < I915_NUM_ENGINES; i++) {
for (i = 0; i < I915_NUM_ENGINES; i++) {
if (id >= I915_NUM_ENGINES)
u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
} engine[I915_NUM_ENGINES];
} *active_bo[I915_NUM_ENGINES], *pinned_bo;
u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
struct i915_address_space *active_vm[I915_NUM_ENGINES];
#define I915_RESET_ENGINE (I915_WEDGED - I915_NUM_ENGINES)
u32 reset_engine_count[I915_NUM_ENGINES];
BUILD_BUG_ON(KSYNCMAP < I915_NUM_ENGINES);
u32 global_sync[I915_NUM_ENGINES];
BUILD_BUG_ON(I915_NUM_ENGINES >
GENMASK(sizeof(mask) * BITS_PER_BYTE - 1, I915_NUM_ENGINES));
struct guc_preempt_work preempt_work[I915_NUM_ENGINES];
I915_NUM_ENGINES > GUC_WQ_SIZE);
u64 submissions[I915_NUM_ENGINES];
if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES)
const u32 hw_engine_mask[I915_NUM_ENGINES] = {
const u32 hw_engine_mask[I915_NUM_ENGINES] = {
BUILD_BUG_ON(VECS2 + 1 != I915_NUM_ENGINES);