I915_MAX_PIPES
struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
u32 de_irq_mask[I915_MAX_PIPES];
u32 pipestat_irq_mask[I915_MAX_PIPES];
struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
int min_cdclk[I915_MAX_PIPES];
u8 min_voltage_level[I915_MAX_PIPES];
u32 chv_dpll_md[I915_MAX_PIPES];
struct intel_encoder *av_enc_map[I915_MAX_PIPES];
BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES >
u32 iir, u32 pipe_stats[I915_MAX_PIPES])
u16 iir, u32 pipe_stats[I915_MAX_PIPES])
u32 iir, u32 pipe_stats[I915_MAX_PIPES])
u32 iir, u32 pipe_stats[I915_MAX_PIPES])
u32 pipe_stats[I915_MAX_PIPES])
u32 pipe_stats[I915_MAX_PIPES] = {};
u32 pipe_stats[I915_MAX_PIPES] = {};
u32 pipe_stats[I915_MAX_PIPES] = {};
u32 pipe_stats[I915_MAX_PIPES] = {};
u32 pipe_stats[I915_MAX_PIPES] = {};
u8 num_sprites[I915_MAX_PIPES];
u8 num_scalers[I915_MAX_PIPES];
int palette_offsets[I915_MAX_PIPES];
int cursor_offsets[I915_MAX_PIPES];
const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
u64 put_domains[I915_MAX_PIPES] = {};
} cursor[I915_MAX_PIPES];
} pipe[I915_MAX_PIPES];
} plane[I915_MAX_PIPES];
struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
int min_cdclk[I915_MAX_PIPES];
u8 min_voltage_level[I915_MAX_PIPES];
u32 dpll[I915_MAX_PIPES];