HZ
_CITRUS_STDENC_DECLS(HZ);
_CITRUS_STDENC_DEF_OPS(HZ);
_CITRUS_STDENC_GETOPS_FUNC(HZ);
#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
end_jiffies = (utimeout * HZ / 1000) + jiffies;
unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
end_jiffies = (utimeout * HZ / 1000) + jiffies;
unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
&commit->flip_done, 10*HZ);
ret = wait_for_completion_timeout(&commit->flip_done, 10 * HZ);
10*HZ);
10*HZ);
10*HZ);
10*HZ);
10*HZ);
10*HZ);
10*HZ);
(4 * HZ));
.delay = HZ / 20,
#define DRM_OUTPUT_POLL_PERIOD (10*HZ)
delay = HZ;
jiffies + ((drm_vblank_offdelay * HZ)/1000));
DRM_WAIT_ON(ret, vblank->queue, 3 * HZ,
#define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
#define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
#define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
#define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
#define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */
#define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
if (NSEC_PER_SEC % HZ &&
div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
round_jiffies_up_relative(HZ));
round_jiffies_up_relative(HZ));
if (i915_gem_wait_for_idle(i915, I915_WAIT_LOCKED, HZ / 5)) {
err_printf(m, "Epoch: %lu jiffies (%u HZ)\n", error->epoch, HZ);
i915_wedge_on_timeout(&w, dev_priv, 5*HZ) {
5 * HZ, 10);
schedule_timeout((HZ/100 > 1) ? HZ/100 : 1); \
return j * (NSEC_PER_SEC / HZ);
return j * (USEC_PER_SEC / HZ);
#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
r = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, 30 * HZ);
ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, 30 * HZ);
long timeout = 15 * HZ;
30 * HZ);
((HZ / 100) < 1) ? 1 : HZ / 100);
30 * HZ);
((HZ / 100) < 1) ? 1 : HZ / 100);
((HZ / 100) < 1) ? 1 : HZ / 100);