sys/bus/u4b/uvc/uvc_ctrls.c

593

item_num = ARRAY_SIZE(exposure_mode_menu);

sys/bus/u4b/uvc/uvc_ctrls.c

598

item_num = ARRAY_SIZE(power_line_freq_menu);

sys/dev/drm/amd/amdgpu/amdgpu_afmt.c

94

for (i = 0; i < ARRAY_SIZE(amdgpu_afmt_predefined_acr); i++) {

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

121

ARRAY_SIZE(adev->gfx.config.tile_mode_array);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

125

ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

160

ARRAY_SIZE(adev->gfx.config.tile_mode_array);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

164

ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

360

if (con_obj_id >= ARRAY_SIZE(object_connector_convert)) {

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

831

for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

847

for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

930

ARRAY_SIZE(amdgpu_debugfs_list));

sys/dev/drm/amd/amdgpu/amdgpu_device.c

2115

for (i = 0; i < ARRAY_SIZE(ip_order); i++) {

sys/dev/drm/amd/amdgpu/amdgpu_device.c

2149

for (i = 0; i < ARRAY_SIZE(ip_order); i++) {

sys/dev/drm/amd/amdgpu/amdgpu_display.c

599

sz = ARRAY_SIZE(amdgpu_underscan_enum_list);

sys/dev/drm/amd/amdgpu/amdgpu_display.c

617

sz = ARRAY_SIZE(amdgpu_audio_enum_list);

sys/dev/drm/amd/amdgpu/amdgpu_display.c

623

sz = ARRAY_SIZE(amdgpu_dither_enum_list);

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

901

} else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

1215

const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

1399

ARRAY_SIZE(amdgpu_firmware_info_list));

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

2304

return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

408

if (ret || idx >= ARRAY_SIZE(data.states)) {

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

412

idx = array_index_nospec(idx, ARRAY_SIZE(data.states));

sys/dev/drm/amd/amdgpu/amdgpu_ttm.c

2557

for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {

sys/dev/drm/amd/amdgpu/amdgpu_ttm.c

2572

count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);

sys/dev/drm/amd/amdgpu/amdgpu_ttm.c

2590

for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++)

sys/dev/drm/amd/amdgpu/atombios_dp.c

278

for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {

sys/dev/drm/amd/amdgpu/cik.c

1128

for (i = 0; i < ARRAY_SIZE(cik_allowed_read_registers); i++) {

sys/dev/drm/amd/amdgpu/cik.c

759

ARRAY_SIZE(bonaire_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/cik.c

762

ARRAY_SIZE(bonaire_golden_registers));

sys/dev/drm/amd/amdgpu/cik.c

765

ARRAY_SIZE(bonaire_golden_common_registers));

sys/dev/drm/amd/amdgpu/cik.c

768

ARRAY_SIZE(bonaire_golden_spm_registers));

sys/dev/drm/amd/amdgpu/cik.c

773

ARRAY_SIZE(kalindi_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/cik.c

776

ARRAY_SIZE(kalindi_golden_registers));

sys/dev/drm/amd/amdgpu/cik.c

779

ARRAY_SIZE(kalindi_golden_common_registers));

sys/dev/drm/amd/amdgpu/cik.c

782

ARRAY_SIZE(kalindi_golden_spm_registers));

sys/dev/drm/amd/amdgpu/cik.c

787

ARRAY_SIZE(kalindi_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/cik.c

790

ARRAY_SIZE(godavari_golden_registers));

sys/dev/drm/amd/amdgpu/cik.c

793

ARRAY_SIZE(kalindi_golden_common_registers));

sys/dev/drm/amd/amdgpu/cik.c

796

ARRAY_SIZE(kalindi_golden_spm_registers));

sys/dev/drm/amd/amdgpu/cik.c

801

ARRAY_SIZE(spectre_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/cik.c

804

ARRAY_SIZE(spectre_golden_registers));

sys/dev/drm/amd/amdgpu/cik.c

807

ARRAY_SIZE(spectre_golden_common_registers));

sys/dev/drm/amd/amdgpu/cik.c

810

ARRAY_SIZE(spectre_golden_spm_registers));

sys/dev/drm/amd/amdgpu/cik.c

815

ARRAY_SIZE(hawaii_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/cik.c

818

ARRAY_SIZE(hawaii_golden_registers));

sys/dev/drm/amd/amdgpu/cik.c

821

ARRAY_SIZE(hawaii_golden_common_registers));

sys/dev/drm/amd/amdgpu/cik.c

824

ARRAY_SIZE(hawaii_golden_spm_registers));

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1354

for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {

sys/dev/drm/amd/amdgpu/dce_v10_0.c

153

ARRAY_SIZE(fiji_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/dce_v10_0.c

156

ARRAY_SIZE(golden_settings_fiji_a10));

sys/dev/drm/amd/amdgpu/dce_v10_0.c

161

ARRAY_SIZE(tonga_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/dce_v10_0.c

164

ARRAY_SIZE(golden_settings_tonga_a11));

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1380

for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {

sys/dev/drm/amd/amdgpu/dce_v11_0.c

162

ARRAY_SIZE(cz_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/dce_v11_0.c

165

ARRAY_SIZE(cz_golden_settings_a11));

sys/dev/drm/amd/amdgpu/dce_v11_0.c

170

ARRAY_SIZE(stoney_golden_settings_a11));

sys/dev/drm/amd/amdgpu/dce_v11_0.c

176

ARRAY_SIZE(polaris11_golden_settings_a11));

sys/dev/drm/amd/amdgpu/dce_v11_0.c

182

ARRAY_SIZE(polaris10_golden_settings_a11));

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1307

for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {

sys/dev/drm/amd/amdgpu/df_v3_6.c

67

if (fb_channel_number >= ARRAY_SIZE(df_v3_6_channel_number))

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1025

ARRAY_SIZE(adev->gfx.config.tile_mode_array);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1027

ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3292

(u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3296

(u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1639

(((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1641

(((ARRAY_SIZE(sgpr1_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1643

(((ARRAY_SIZE(sgpr2_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1659

for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1662

for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1670

for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1696

for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) {

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1722

for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) {

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1770

for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

2202

const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

2203

const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4045

ARRAY_SIZE(unique_indices),

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4048

ARRAY_SIZE(indirect_start_offsets));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4070

for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4077

for (i = 0; i < ARRAY_SIZE(unique_indices); i++) {

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

735

ARRAY_SIZE(iceland_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

738

ARRAY_SIZE(golden_settings_iceland_a11));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

741

ARRAY_SIZE(iceland_golden_common_all));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

746

ARRAY_SIZE(fiji_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

749

ARRAY_SIZE(golden_settings_fiji_a10));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

752

ARRAY_SIZE(fiji_golden_common_all));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

758

ARRAY_SIZE(tonga_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

761

ARRAY_SIZE(golden_settings_tonga_a11));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

764

ARRAY_SIZE(tonga_golden_common_all));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

769

ARRAY_SIZE(golden_settings_vegam_a11));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

772

ARRAY_SIZE(vegam_golden_common_all));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

778

ARRAY_SIZE(golden_settings_polaris11_a11));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

781

ARRAY_SIZE(polaris11_golden_common_all));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

786

ARRAY_SIZE(golden_settings_polaris10_a11));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

789

ARRAY_SIZE(polaris10_golden_common_all));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

802

ARRAY_SIZE(cz_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

805

ARRAY_SIZE(cz_golden_settings_a11));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

808

ARRAY_SIZE(cz_golden_common_all));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

813

ARRAY_SIZE(stoney_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

816

ARRAY_SIZE(stoney_golden_settings_a11));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

819

ARRAY_SIZE(stoney_golden_common_all));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2141

unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2149

ARRAY_SIZE(indirect_start_offsets));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2204

for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2209

for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) {

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

308

ARRAY_SIZE(golden_settings_gc_9_0));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

311

ARRAY_SIZE(golden_settings_gc_9_0_vg10));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

316

ARRAY_SIZE(golden_settings_gc_9_2_1));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

319

ARRAY_SIZE(golden_settings_gc_9_2_1_vg12));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

324

ARRAY_SIZE(golden_settings_gc_9_0));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

327

ARRAY_SIZE(golden_settings_gc_9_0_vg20));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

331

ARRAY_SIZE(golden_settings_gc_9_1));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

335

ARRAY_SIZE(golden_settings_gc_9_1_rv2));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

339

ARRAY_SIZE(golden_settings_gc_9_1_rv1));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

346

(const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

77

ARRAY_SIZE(iceland_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

80

ARRAY_SIZE(golden_settings_iceland_a11));

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

826

for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

843

for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

132

ARRAY_SIZE(fiji_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

135

ARRAY_SIZE(golden_settings_fiji_a10));

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

140

ARRAY_SIZE(tonga_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

143

ARRAY_SIZE(golden_settings_tonga_a11));

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

150

ARRAY_SIZE(golden_settings_polaris11_a11));

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

155

ARRAY_SIZE(golden_settings_polaris10_a11));

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

160

ARRAY_SIZE(cz_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

165

ARRAY_SIZE(stoney_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

168

ARRAY_SIZE(golden_settings_stoney_common));

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

1065

ARRAY_SIZE(golden_settings_mmhub_1_0_0));

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

1068

ARRAY_SIZE(golden_settings_athub_1_0_0));

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

1075

ARRAY_SIZE(golden_settings_athub_1_0_0));

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

1095

ARRAY_SIZE(golden_settings_vega10_hdp));

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

630

for (i = 0; i < ARRAY_SIZE(ecc_umclocalcap_addrs); ++i) {

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

648

for (i = 0; i < ARRAY_SIZE(ecc_umcch_umc_config_addrs); ++i) {

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

667

for (i = 0; i < ARRAY_SIZE(ecc_umcch_eccctrl_addrs); ++i) {

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

284

ARRAY_SIZE(

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

288

ARRAY_SIZE(

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

292

ARRAY_SIZE(

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

298

ARRAY_SIZE(

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

302

ARRAY_SIZE(

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

306

ARRAY_SIZE(

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

100

ARRAY_SIZE(iceland_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

103

ARRAY_SIZE(golden_settings_iceland_a11));

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

201

ARRAY_SIZE(fiji_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

204

ARRAY_SIZE(golden_settings_fiji_a10));

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

209

ARRAY_SIZE(tonga_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

212

ARRAY_SIZE(golden_settings_tonga_a11));

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

219

ARRAY_SIZE(golden_settings_polaris11_a11));

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

224

ARRAY_SIZE(golden_settings_polaris10_a11));

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

229

ARRAY_SIZE(cz_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

232

ARRAY_SIZE(cz_golden_settings_a11));

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

237

ARRAY_SIZE(stoney_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

240

ARRAY_SIZE(stoney_golden_settings_a11));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

210

ARRAY_SIZE(golden_settings_sdma_4));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

213

ARRAY_SIZE(golden_settings_sdma_vg10));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

218

ARRAY_SIZE(golden_settings_sdma_4));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

221

ARRAY_SIZE(golden_settings_sdma_vg12));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

226

ARRAY_SIZE(golden_settings_sdma0_4_2_init));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

229

ARRAY_SIZE(golden_settings_sdma0_4_2));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

232

ARRAY_SIZE(golden_settings_sdma1_4_2));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

237

ARRAY_SIZE(golden_settings_sdma_4_1));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

241

ARRAY_SIZE(golden_settings_sdma_rv2));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

245

ARRAY_SIZE(golden_settings_sdma_rv1));

sys/dev/drm/amd/amdgpu/soc15.c

338

for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {

sys/dev/drm/amd/amdgpu/vi.c

286

ARRAY_SIZE(iceland_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/vi.c

291

ARRAY_SIZE(fiji_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/vi.c

296

ARRAY_SIZE(tonga_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/vi.c

301

ARRAY_SIZE(cz_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/vi.c

306

ARRAY_SIZE(stoney_mgcg_cgcg_init));

sys/dev/drm/amd/amdgpu/vi.c

652

for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) {

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3653

ARRAY_SIZE(rgb_formats),

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3663

ARRAY_SIZE(yuv_formats),

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3673

ARRAY_SIZE(cursor_formats),

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3853

n = ARRAY_SIZE(common_modes);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

710

for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) {

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1269

audio_array_size = ARRAY_SIZE(

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1274

audio_array_size = ARRAY_SIZE(

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1279

audio_array_size = ARRAY_SIZE(

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1115

for (i = 0; i < ARRAY_SIZE(global_color_matrix); ++i) {

sys/dev/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

693

for (i = 0; i < ARRAY_SIZE(global_color_matrix); ++i) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1108

audio_array_size = ARRAY_SIZE(

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1113

audio_array_size = ARRAY_SIZE(

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1118

audio_array_size = ARRAY_SIZE(

sys/dev/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c

102

ARRAY_SIZE(dce100_aux_regs),

sys/dev/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c

323

ARRAY_SIZE(dce110_aux_regs),

sys/dev/drm/amd/display/dc/i2caux/dce112/i2caux_dce112.c

96

ARRAY_SIZE(dce112_aux_regs),

sys/dev/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c

116

ARRAY_SIZE(dce120_aux_regs),

sys/dev/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c

245

} while (i < ARRAY_SIZE(hw_ddc_lines));

sys/dev/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c

266

} while (i < ARRAY_SIZE(hw_aux_lines));

sys/dev/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c

116

ARRAY_SIZE(dcn10_aux_regs),

sys/dev/drm/amd/display/modules/color/color_gamma.c

267

} while (i != ARRAY_SIZE(coefficients->a0));

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

448

ARRAY_SIZE(VddDcfClk),

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

451

ARRAY_SIZE(VddSocClk),

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

454

ARRAY_SIZE(VddFClk),

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

458

ARRAY_SIZE(VddDispClk),

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

461

ARRAY_SIZE(VddDppClk), &VddDppClk[0]);

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

463

ARRAY_SIZE(VddPhyClk), &VddPhyClk[0]);

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

911

PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number),

sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c

531

execute_pwr_table(hwmgr, pwr_virus_table_pre, ARRAY_SIZE(pwr_virus_table_pre));

sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c

538

execute_pwr_table(hwmgr, pwr_virus_table_post, ARRAY_SIZE(pwr_virus_table_post));

sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c

562

for (i = 0; i < ARRAY_SIZE(firmware_list); i++) {

sys/dev/drm/drm_atomic.c

1186

ARRAY_SIZE(drm_atomic_debugfs_list),

sys/dev/drm/drm_blend.c

268

props, ARRAY_SIZE(props),

sys/dev/drm/drm_blend.c

574

for (i = 0; i < ARRAY_SIZE(props); i++) {

sys/dev/drm/drm_color_mgmt.c

377

if (WARN_ON(encoding >= ARRAY_SIZE(color_encoding_name)))

sys/dev/drm/drm_color_mgmt.c

392

if (WARN_ON(range >= ARRAY_SIZE(color_range_name)))

sys/dev/drm/drm_connector.c

102

for (i = 0; i < ARRAY_SIZE(drm_connector_enum_list); i++)

sys/dev/drm/drm_connector.c

1029

ARRAY_SIZE(drm_dvi_i_select_enum_list));

sys/dev/drm/drm_connector.c

1035

ARRAY_SIZE(drm_dvi_i_subconnector_enum_list));

sys/dev/drm/drm_connector.c

110

for (i = 0; i < ARRAY_SIZE(drm_connector_enum_list); i++)

sys/dev/drm/drm_connector.c

1146

ARRAY_SIZE(drm_tv_select_enum_list));

sys/dev/drm/drm_connector.c

1156

ARRAY_SIZE(drm_tv_subconnector_enum_list));

sys/dev/drm/drm_connector.c

1251

ARRAY_SIZE(drm_scaling_mode_enum_list));

sys/dev/drm/drm_connector.c

1280

(1U << ARRAY_SIZE(drm_scaling_mode_enum_list)) - 1;

sys/dev/drm/drm_connector.c

1293

for (i = 0; i < ARRAY_SIZE(drm_scaling_mode_enum_list); i++) {

sys/dev/drm/drm_connector.c

1342

ARRAY_SIZE(drm_cp_enum_list));

sys/dev/drm/drm_connector.c

1373

ARRAY_SIZE(drm_aspect_ratio_enum_list));

sys/dev/drm/drm_connector.c

1400

ARRAY_SIZE(drm_content_type_enum_list));

sys/dev/drm/drm_connector.c

1625

ARRAY_SIZE(drm_panel_orientation_enum_list));

sys/dev/drm/drm_connector.c

329

for (i = 0; i < ARRAY_SIZE(connector->encoder_ids); i++) {

sys/dev/drm/drm_connector.c

975

ARRAY_SIZE(drm_dpms_enum_list));

sys/dev/drm/drm_connector.c

998

ARRAY_SIZE(drm_link_status_enum_list));

sys/dev/drm/drm_dp_dual_mode_helper.c

79

ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));

sys/dev/drm/drm_dp_dual_mode_helper.c

82

if (ret != ARRAY_SIZE(msgs))

sys/dev/drm/drm_dp_helper.c

1201

if (i >= ARRAY_SIZE(psr_setup_time_us))

sys/dev/drm/drm_dp_helper.c

1302

for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {

sys/dev/drm/drm_edid.c

1822

for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {

sys/dev/drm/drm_edid.c

1914

for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {

sys/dev/drm/drm_edid.c

2232

for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {

sys/dev/drm/drm_edid.c

2459

for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {

sys/dev/drm/drm_edid.c

2494

for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {

sys/dev/drm/drm_edid.c

2523

for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {

sys/dev/drm/drm_edid.c

2606

if (m >= ARRAY_SIZE(est3_modes))

sys/dev/drm/drm_edid.c

2987

for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {

sys/dev/drm/drm_edid.c

3026

for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {

sys/dev/drm/drm_edid.c

3050

return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);

sys/dev/drm/drm_edid.c

3092

for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {

sys/dev/drm/drm_edid.c

3127

for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {

sys/dev/drm/drm_edid.c

3145

return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);

sys/dev/drm/drm_edid.c

3382

for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {

sys/dev/drm/drm_edid.c

4815

count = ARRAY_SIZE(drm_dmt_modes);

sys/dev/drm/drm_fourcc.c

232

for (i = 0; i < ARRAY_SIZE(formats); ++i) {

sys/dev/drm/drm_framebuffer.c

1099

ARRAY_SIZE(drm_framebuffer_debugfs_list),

sys/dev/drm/drm_ioctl.c

709

#define DRM_CORE_IOCTL_COUNT ARRAY_SIZE( drm_ioctls )

sys/dev/drm/drm_mode_config.c

223

ARRAY_SIZE(drm_plane_type_enum_list));

sys/dev/drm/drm_modes.c

1268

if (WARN_ON(index < 0 || index >= ARRAY_SIZE(drm_mode_status_names)))

sys/dev/drm/drm_modeset_helper.c

129

ARRAY_SIZE(safe_modeset_formats),

sys/dev/drm/drm_scdc_helper.c

71

ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));

sys/dev/drm/drm_scdc_helper.c

74

if (ret != ARRAY_SIZE(msgs))

sys/dev/drm/i915/dvo_ch7xxx.c

114

for (i = 0; i < ARRAY_SIZE(ch7xxx_ids); i++) {

sys/dev/drm/i915/dvo_ch7xxx.c

126

for (i = 0; i < ARRAY_SIZE(ch7xxx_dids); i++) {

sys/dev/drm/i915/dvo_ivch.c

181

u16 reg_backup[ARRAY_SIZE(backup_addresses)];

sys/dev/drm/i915/dvo_ivch.c

298

for (i = 0; i < ARRAY_SIZE(backup_addresses); i++)

sys/dev/drm/i915/dvo_ivch.c

337

for (i = 0; i < ARRAY_SIZE(backup_addresses); i++)

sys/dev/drm/i915/dvo_ivch.c

407

vr10 = priv->reg_backup[ARRAY_SIZE(backup_addresses) - 1];

sys/dev/drm/i915/dvo_ns2501.c

600

for (i = 0; i < ARRAY_SIZE(regs_init); i++)

sys/dev/drm/i915/dvo_ns2501.c

604

for (i = 0; i < ARRAY_SIZE(mode_agnostic_values); i++)

sys/dev/drm/i915/i915_cmd_parser.c

467

{ common_cmds, ARRAY_SIZE(common_cmds) },

sys/dev/drm/i915/i915_cmd_parser.c

468

{ render_cmds, ARRAY_SIZE(render_cmds) },

sys/dev/drm/i915/i915_cmd_parser.c

472

{ common_cmds, ARRAY_SIZE(common_cmds) },

sys/dev/drm/i915/i915_cmd_parser.c

473

{ render_cmds, ARRAY_SIZE(render_cmds) },

sys/dev/drm/i915/i915_cmd_parser.c

474

{ hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) },

sys/dev/drm/i915/i915_cmd_parser.c

478

{ common_cmds, ARRAY_SIZE(common_cmds) },

sys/dev/drm/i915/i915_cmd_parser.c

479

{ video_cmds, ARRAY_SIZE(video_cmds) },

sys/dev/drm/i915/i915_cmd_parser.c

483

{ common_cmds, ARRAY_SIZE(common_cmds) },

sys/dev/drm/i915/i915_cmd_parser.c

484

{ vecs_cmds, ARRAY_SIZE(vecs_cmds) },

sys/dev/drm/i915/i915_cmd_parser.c

488

{ common_cmds, ARRAY_SIZE(common_cmds) },

sys/dev/drm/i915/i915_cmd_parser.c

489

{ blt_cmds, ARRAY_SIZE(blt_cmds) },

sys/dev/drm/i915/i915_cmd_parser.c

493

{ common_cmds, ARRAY_SIZE(common_cmds) },

sys/dev/drm/i915/i915_cmd_parser.c

494

{ blt_cmds, ARRAY_SIZE(blt_cmds) },

sys/dev/drm/i915/i915_cmd_parser.c

495

{ hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },

sys/dev/drm/i915/i915_cmd_parser.c

636

{ gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false },

sys/dev/drm/i915/i915_cmd_parser.c

637

{ ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true },

sys/dev/drm/i915/i915_cmd_parser.c

641

{ gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false },

sys/dev/drm/i915/i915_cmd_parser.c

642

{ ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true },

sys/dev/drm/i915/i915_cmd_parser.c

646

{ gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false },

sys/dev/drm/i915/i915_cmd_parser.c

647

{ hsw_render_regs, ARRAY_SIZE(hsw_render_regs), false },

sys/dev/drm/i915/i915_cmd_parser.c

648

{ hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true },

sys/dev/drm/i915/i915_cmd_parser.c

652

{ gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false },

sys/dev/drm/i915/i915_cmd_parser.c

653

{ hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true },

sys/dev/drm/i915/i915_cmd_parser.c

876

ARRAY_SIZE(hsw_render_ring_cmds);

sys/dev/drm/i915/i915_cmd_parser.c

879

cmd_table_count = ARRAY_SIZE(gen7_render_cmds);

sys/dev/drm/i915/i915_cmd_parser.c

884

engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables);

sys/dev/drm/i915/i915_cmd_parser.c

887

engine->reg_table_count = ARRAY_SIZE(ivb_render_reg_tables);

sys/dev/drm/i915/i915_cmd_parser.c

894

cmd_table_count = ARRAY_SIZE(gen7_video_cmds);

sys/dev/drm/i915/i915_cmd_parser.c

900

cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds);

sys/dev/drm/i915/i915_cmd_parser.c

903

cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);

sys/dev/drm/i915/i915_cmd_parser.c

908

engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables);

sys/dev/drm/i915/i915_cmd_parser.c

911

engine->reg_table_count = ARRAY_SIZE(ivb_blt_reg_tables);

sys/dev/drm/i915/i915_cmd_parser.c

918

cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds);

sys/dev/drm/i915/i915_drv.c

2655

for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)

sys/dev/drm/i915/i915_drv.c

2699

for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)

sys/dev/drm/i915/i915_drv.c

2737

for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)

sys/dev/drm/i915/i915_drv.c

2781

for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)

sys/dev/drm/i915/i915_drv.c

3303

.num_ioctls = ARRAY_SIZE(i915_ioctls),

sys/dev/drm/i915/i915_gem.c

3161

if (n_pages > ARRAY_SIZE(stack_pages)) {

sys/dev/drm/i915/i915_gem_batch_pool.c

40

for (n = 0; n < ARRAY_SIZE(pool->cache_list); n++)

sys/dev/drm/i915/i915_gem_batch_pool.c

56

for (n = 0; n < ARRAY_SIZE(pool->cache_list); n++) {

sys/dev/drm/i915/i915_gem_batch_pool.c

96

if (n >= ARRAY_SIZE(pool->cache_list))

sys/dev/drm/i915/i915_gem_batch_pool.c

97

n = ARRAY_SIZE(pool->cache_list) - 1;

sys/dev/drm/i915/i915_gem_context.c

217

for (n = 0; n < ARRAY_SIZE(ctx->__engine); n++) {

sys/dev/drm/i915/i915_gem_context.c

342

for (n = 0; n < ARRAY_SIZE(ctx->__engine); n++) {

sys/dev/drm/i915/i915_gem_execbuffer.c

1469

min_t(unsigned int, remain, ARRAY_SIZE(stack));

sys/dev/drm/i915/i915_gem_execbuffer.c

1526

urelocs += ARRAY_SIZE(stack);

sys/dev/drm/i915/i915_gem_gtt.c

3807

for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) {

sys/dev/drm/i915/i915_gpu_error.c

1567

BUILD_BUG_ON(ARRAY_SIZE(error->engine) > ARRAY_SIZE(error->active_bo));

sys/dev/drm/i915/i915_gpu_error.c

1568

BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_vm));

sys/dev/drm/i915/i915_gpu_error.c

1569

BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_bo_count));

sys/dev/drm/i915/i915_gpu_error.c

1572

for (i = 0; i < ARRAY_SIZE(error->engine); i++) {

sys/dev/drm/i915/i915_gpu_error.c

1789

for (i = 0; i < ARRAY_SIZE(error->engine); i++) {

sys/dev/drm/i915/i915_gpu_error.c

677

for (i = 0; i < ARRAY_SIZE(error->engine); i++) {

sys/dev/drm/i915/i915_gpu_error.c

734

for (i = 0; i < ARRAY_SIZE(error->engine); i++) {

sys/dev/drm/i915/i915_gpu_error.c

739

for (i = 0; i < ARRAY_SIZE(error->active_vm); i++) {

sys/dev/drm/i915/i915_gpu_error.c

747

for (j = 0; j < ARRAY_SIZE(error->engine); j++) {

sys/dev/drm/i915/i915_gpu_error.c

766

for (i = 0; i < ARRAY_SIZE(error->engine); i++) {

sys/dev/drm/i915/i915_gpu_error.c

923

for (i = 0; i < ARRAY_SIZE(error->engine); i++) {

sys/dev/drm/i915/i915_gpu_error.c

942

for (i = 0; i < ARRAY_SIZE(error->active_bo); i++)

sys/dev/drm/i915/i915_oa_cflgt3.c

93

dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);

sys/dev/drm/i915/i915_oa_cflgt3.c

96

dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);

sys/dev/drm/i915/i915_oa_cflgt3.c

99

dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);

sys/dev/drm/i915/i915_oa_cnl.c

105

dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);

sys/dev/drm/i915/i915_oa_cnl.c

108

dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);

sys/dev/drm/i915/i915_oa_cnl.c

111

dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);

sys/dev/drm/i915/i915_oa_hsw.c

123

dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_render_basic);

sys/dev/drm/i915/i915_oa_hsw.c

126

dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_render_basic);

sys/dev/drm/i915/i915_oa_hsw.c

129

dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_render_basic);

sys/dev/drm/i915/i915_oa_icl.c

102

dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);

sys/dev/drm/i915/i915_oa_icl.c

105

dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);

sys/dev/drm/i915/i915_oa_icl.c

108

dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);

sys/dev/drm/i915/i915_perf.c

1659

for (i = 0; i < ARRAY_SIZE(flex_regs); i++) {

sys/dev/drm/i915/i915_perf.c

2978

for (i = 0; i < ARRAY_SIZE(flex_eu_regs); i++) {

sys/dev/drm/i915/i915_pmu.c

852

for (i = 0; i < ARRAY_SIZE(events); i++) {

sys/dev/drm/i915/i915_pmu.c

858

for (i = 0; i < ARRAY_SIZE(engine_events); i++) {

sys/dev/drm/i915/i915_pmu.c

884

for (i = 0; i < ARRAY_SIZE(events); i++) {

sys/dev/drm/i915/i915_pmu.c

909

for (i = 0; i < ARRAY_SIZE(engine_events); i++) {

sys/dev/drm/i915/i915_query.c

122

if (func_idx < ARRAY_SIZE(i915_query_funcs)) {

sys/dev/drm/i915/i915_query.c

124

ARRAY_SIZE(i915_query_funcs));

sys/dev/drm/i915/i915_selftest.h

75

__i915_subtests(__func__, T, ARRAY_SIZE(T), data)

sys/dev/drm/i915/i915_vma.c

42

.max_entries = ARRAY_SIZE(entries),

sys/dev/drm/i915/intel_audio.c

119

for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {

sys/dev/drm/i915/intel_audio.c

193

for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {

sys/dev/drm/i915/intel_audio.c

198

if (i == ARRAY_SIZE(hdmi_audio_clock)) {

sys/dev/drm/i915/intel_audio.c

218

for (i = 0; i < ARRAY_SIZE(hdmi_aud_ncts); i++) {

sys/dev/drm/i915/intel_audio.c

814

if (WARN_ON(pipe >= ARRAY_SIZE(dev_priv->av_enc_map)))

sys/dev/drm/i915/intel_audio.c

937

for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)

sys/dev/drm/i915/intel_bios.c

1178

if (val >= ARRAY_SIZE(mapping)) {

sys/dev/drm/i915/intel_bios.c

1280

n_entries = ARRAY_SIZE(icp_ddc_pin_map);

sys/dev/drm/i915/intel_bios.c

1283

n_entries = ARRAY_SIZE(cnp_ddc_pin_map);

sys/dev/drm/i915/intel_bios.c

1913

if (WARN_ON(port == PORT_A) || port >= ARRAY_SIZE(port_mapping))

sys/dev/drm/i915/intel_bios.c

193

if (index >= ARRAY_SIZE(ptrs->ptr))

sys/dev/drm/i915/intel_bios.c

1986

if (port == PORT_A || port >= ARRAY_SIZE(port_mapping))

sys/dev/drm/i915/intel_cdclk.c

266

if (cdclk_sel >= ARRAY_SIZE(div_3200))

sys/dev/drm/i915/intel_cdclk.c

346

if (cdclk_sel >= ARRAY_SIZE(div_3200))

sys/dev/drm/i915/intel_color.c

169

for (i = 0; i < ARRAY_SIZE(coeffs); i++) {

sys/dev/drm/i915/intel_color.c

268

for (i = 0; i < ARRAY_SIZE(coeffs); i++) {

sys/dev/drm/i915/intel_csr.c

202

size = ARRAY_SIZE(skl_stepping_info);

sys/dev/drm/i915/intel_csr.c

205

size = ARRAY_SIZE(bxt_stepping_info);

sys/dev/drm/i915/intel_csr.c

386

if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {

sys/dev/drm/i915/intel_ddi.c

1150

for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {

sys/dev/drm/i915/intel_ddi.c

1200

if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {

sys/dev/drm/i915/intel_ddi.c

2242

n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);

sys/dev/drm/i915/intel_ddi.c

2262

if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))

sys/dev/drm/i915/intel_ddi.c

2263

n_entries = ARRAY_SIZE(index_to_dp_signal_levels);

sys/dev/drm/i915/intel_ddi.c

2558

n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);

sys/dev/drm/i915/intel_ddi.c

2685

for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {

sys/dev/drm/i915/intel_ddi.c

619

*n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);

sys/dev/drm/i915/intel_ddi.c

622

*n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);

sys/dev/drm/i915/intel_ddi.c

631

*n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);

sys/dev/drm/i915/intel_ddi.c

634

*n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);

sys/dev/drm/i915/intel_ddi.c

637

*n_entries = ARRAY_SIZE(skl_ddi_translations_dp);

sys/dev/drm/i915/intel_ddi.c

646

*n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);

sys/dev/drm/i915/intel_ddi.c

649

*n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);

sys/dev/drm/i915/intel_ddi.c

652

*n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);

sys/dev/drm/i915/intel_ddi.c

662

*n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);

sys/dev/drm/i915/intel_ddi.c

666

*n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);

sys/dev/drm/i915/intel_ddi.c

669

*n_entries = ARRAY_SIZE(skl_ddi_translations_edp);

sys/dev/drm/i915/intel_ddi.c

684

*n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);

sys/dev/drm/i915/intel_ddi.c

687

*n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);

sys/dev/drm/i915/intel_ddi.c

716

*n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);

sys/dev/drm/i915/intel_ddi.c

719

*n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);

sys/dev/drm/i915/intel_ddi.c

739

*n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);

sys/dev/drm/i915/intel_ddi.c

752

*n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);

sys/dev/drm/i915/intel_ddi.c

755

*n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);

sys/dev/drm/i915/intel_ddi.c

770

*n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);

sys/dev/drm/i915/intel_ddi.c

773

*n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);

sys/dev/drm/i915/intel_ddi.c

784

*n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);

sys/dev/drm/i915/intel_ddi.c

792

*n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);

sys/dev/drm/i915/intel_ddi.c

802

*n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);

sys/dev/drm/i915/intel_ddi.c

812

*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);

sys/dev/drm/i915/intel_ddi.c

815

*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);

sys/dev/drm/i915/intel_ddi.c

818

*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);

sys/dev/drm/i915/intel_ddi.c

833

*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);

sys/dev/drm/i915/intel_ddi.c

836

*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);

sys/dev/drm/i915/intel_ddi.c

839

*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);

sys/dev/drm/i915/intel_ddi.c

855

*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);

sys/dev/drm/i915/intel_ddi.c

858

*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);

sys/dev/drm/i915/intel_ddi.c

861

*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);

sys/dev/drm/i915/intel_ddi.c

882

*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);

sys/dev/drm/i915/intel_ddi.c

885

*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);

sys/dev/drm/i915/intel_ddi.c

888

*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);

sys/dev/drm/i915/intel_ddi.c

897

*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);

sys/dev/drm/i915/intel_ddi.c

900

*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);

sys/dev/drm/i915/intel_ddi.c

903

*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);

sys/dev/drm/i915/intel_ddi.c

923

n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);

sys/dev/drm/i915/intel_device_info.c

155

for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++)

sys/dev/drm/i915/intel_device_info.c

65

BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);

sys/dev/drm/i915/intel_device_info.c

67

if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||

sys/dev/drm/i915/intel_device_info.h

196

for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)

sys/dev/drm/i915/intel_display.c

11079

for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {

sys/dev/drm/i915/intel_display.c

13856

num_formats = ARRAY_SIZE(skl_pri_planar_formats);

sys/dev/drm/i915/intel_display.c

13859

num_formats = ARRAY_SIZE(skl_primary_formats);

sys/dev/drm/i915/intel_display.c

13876

num_formats = ARRAY_SIZE(i965_primary_formats);

sys/dev/drm/i915/intel_display.c

13888

num_formats = ARRAY_SIZE(i8xx_primary_formats);

sys/dev/drm/i915/intel_display.c

14020

ARRAY_SIZE(intel_cursor_formats),

sys/dev/drm/i915/intel_display.c

14127

BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||

sys/dev/drm/i915/intel_display.c

14134

BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||

sys/dev/drm/i915/intel_display.c

15129

for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {

sys/dev/drm/i915/intel_display.c

15139

for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {

sys/dev/drm/i915/intel_display.c

2003

for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)

sys/dev/drm/i915/intel_display.c

2474

ARRAY_SIZE(ccs_formats),

sys/dev/drm/i915/intel_display.c

4248

for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {

sys/dev/drm/i915/intel_display.c

8454

if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))

sys/dev/drm/i915/intel_dp.c

1274

for (i = 0; i < ARRAY_SIZE(ch_data); i++)

sys/dev/drm/i915/intel_dp.c

136

for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {

sys/dev/drm/i915/intel_dp.c

1758

count = ARRAY_SIZE(g4x_dpll);

sys/dev/drm/i915/intel_dp.c

1761

count = ARRAY_SIZE(pch_dpll);

sys/dev/drm/i915/intel_dp.c

1764

count = ARRAY_SIZE(chv_dpll);

sys/dev/drm/i915/intel_dp.c

1767

count = ARRAY_SIZE(vlv_dpll);

sys/dev/drm/i915/intel_dp.c

304

for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {

sys/dev/drm/i915/intel_dp.c

337

for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {

sys/dev/drm/i915/intel_dp.c

3955

for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {

sys/dev/drm/i915/intel_dp.c

458

size = ARRAY_SIZE(cnl_rates);

sys/dev/drm/i915/intel_dp.c

465

size = ARRAY_SIZE(bxt_rates);

sys/dev/drm/i915/intel_dp.c

468

size = ARRAY_SIZE(skl_rates);

sys/dev/drm/i915/intel_dp.c

472

size = ARRAY_SIZE(hsw_rates);

sys/dev/drm/i915/intel_dp.c

475

size = ARRAY_SIZE(g4x_rates);

sys/dev/drm/i915/intel_dpio_phy.c

215

*count = ARRAY_SIZE(glk_ddi_phy_info);

sys/dev/drm/i915/intel_dpio_phy.c

218

*count = ARRAY_SIZE(bxt_ddi_phy_info);

sys/dev/drm/i915/intel_dpll_mgr.c

1247

{ even_dividers, ARRAY_SIZE(even_dividers) },

sys/dev/drm/i915/intel_dpll_mgr.c

1248

{ odd_dividers, ARRAY_SIZE(odd_dividers) },

sys/dev/drm/i915/intel_dpll_mgr.c

1256

for (d = 0; d < ARRAY_SIZE(dividers); d++) {

sys/dev/drm/i915/intel_dpll_mgr.c

1257

for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {

sys/dev/drm/i915/intel_dpll_mgr.c

1718

for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {

sys/dev/drm/i915/intel_dpll_mgr.c

2249

for (d = 0; d < ARRAY_SIZE(dividers); d++) {

sys/dev/drm/i915/intel_dpll_mgr.c

2580

n_entries = ARRAY_SIZE(icl_dp_combo_pll_24MHz_values);

sys/dev/drm/i915/intel_dpll_mgr.c

2648

for (i = 0; i < ARRAY_SIZE(div1_vals); i++) {

sys/dev/drm/i915/intel_dsi_vbt.c

212

if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) {

sys/dev/drm/i915/intel_dsi_vbt.c

412

if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id])

sys/dev/drm/i915/intel_dsi_vbt.c

425

if (WARN_ON(seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence)))

sys/dev/drm/i915/intel_dsi_vbt.c

451

if (operation_byte < ARRAY_SIZE(exec_elem))

sys/dev/drm/i915/intel_dvo.c

434

for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) {

sys/dev/drm/i915/intel_engine_cs.c

1592

if (class >= ARRAY_SIZE(user_class_map))

sys/dev/drm/i915/intel_engine_cs.c

271

GEM_BUG_ON(info->class >= ARRAY_SIZE(intel_engine_classes));

sys/dev/drm/i915/intel_engine_cs.c

340

for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {

sys/dev/drm/i915/intel_guc.c

514

return intel_guc_send(guc, action, ARRAY_SIZE(action));

sys/dev/drm/i915/intel_guc.c

535

return intel_guc_send(guc, action, ARRAY_SIZE(action));

sys/dev/drm/i915/intel_guc.c

550

return intel_guc_send(guc, data, ARRAY_SIZE(data));

sys/dev/drm/i915/intel_guc.c

573

return intel_guc_send(guc, data, ARRAY_SIZE(data));

sys/dev/drm/i915/intel_guc.c

588

return intel_guc_send(guc, data, ARRAY_SIZE(data));

sys/dev/drm/i915/intel_guc_ct.c

117

err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);

sys/dev/drm/i915/intel_guc_ct.c

136

err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);

sys/dev/drm/i915/intel_guc_ct.c

198

for (i = 0; i < ARRAY_SIZE(ctch->ctbs); i++) {

sys/dev/drm/i915/intel_guc_ct.c

243

for (i = 0; i < ARRAY_SIZE(ctch->ctbs); i++) {

sys/dev/drm/i915/intel_guc_log.c

48

return intel_guc_send(guc, action, ARRAY_SIZE(action));

sys/dev/drm/i915/intel_guc_log.c

58

return intel_guc_send(guc, action, ARRAY_SIZE(action));

sys/dev/drm/i915/intel_guc_log.c

73

return intel_guc_send(guc, action, ARRAY_SIZE(action));

sys/dev/drm/i915/intel_guc_submission.c

1292

BUILD_BUG_ON(ARRAY_SIZE(engine->execlists.port) *

sys/dev/drm/i915/intel_guc_submission.c

154

return intel_guc_send(guc, action, ARRAY_SIZE(action));

sys/dev/drm/i915/intel_guc_submission.c

164

return intel_guc_send(guc, action, ARRAY_SIZE(action));

sys/dev/drm/i915/intel_guc_submission.c

616

if (WARN_ON(intel_guc_send(guc, data, ARRAY_SIZE(data)))) {

sys/dev/drm/i915/intel_hdmi.c

914

ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));

sys/dev/drm/i915/intel_hdmi.c

915

if (ret == ARRAY_SIZE(msgs))

sys/dev/drm/i915/intel_i2c.c

112

size = ARRAY_SIZE(gmbus_pins_icp);

sys/dev/drm/i915/intel_i2c.c

114

size = ARRAY_SIZE(gmbus_pins_cnp);

sys/dev/drm/i915/intel_i2c.c

116

size = ARRAY_SIZE(gmbus_pins_bxt);

sys/dev/drm/i915/intel_i2c.c

118

size = ARRAY_SIZE(gmbus_pins_skl);

sys/dev/drm/i915/intel_i2c.c

120

size = ARRAY_SIZE(gmbus_pins_bdw);

sys/dev/drm/i915/intel_i2c.c

122

size = ARRAY_SIZE(gmbus_pins);

sys/dev/drm/i915/intel_i2c.c

754

ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);

sys/dev/drm/i915/intel_i2c.c

835

for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {

sys/dev/drm/i915/intel_i2c.c

927

for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {

sys/dev/drm/i915/intel_lrc.c

1583

batch = emit_lri(batch, lri, ARRAY_SIZE(lri));

sys/dev/drm/i915/intel_lrc.c

1748

for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) {

sys/dev/drm/i915/intel_mocs.c

183

table->size = ARRAY_SIZE(skylake_mocs_table);

sys/dev/drm/i915/intel_mocs.c

187

table->size = ARRAY_SIZE(broxton_mocs_table);

sys/dev/drm/i915/intel_modes.c

118

ARRAY_SIZE(broadcast_rgb_names));

sys/dev/drm/i915/intel_modes.c

91

ARRAY_SIZE(force_audio_names));

sys/dev/drm/i915/intel_opregion.c

432

for (i = 0; i < ARRAY_SIZE(power_state_map); i++) {

sys/dev/drm/i915/intel_opregion.c

654

if (i < ARRAY_SIZE(opregion->acpi->didl)) {

sys/dev/drm/i915/intel_opregion.c

657

i -= ARRAY_SIZE(opregion->acpi->didl);

sys/dev/drm/i915/intel_opregion.c

659

if (WARN_ON(i >= ARRAY_SIZE(opregion->acpi->did2)))

sys/dev/drm/i915/intel_opregion.c

722

max_outputs = ARRAY_SIZE(opregion->acpi->didl) +

sys/dev/drm/i915/intel_opregion.c

723

ARRAY_SIZE(opregion->acpi->did2);

sys/dev/drm/i915/intel_opregion.c

773

if (i >= ARRAY_SIZE(opregion->acpi->cadl))

sys/dev/drm/i915/intel_opregion.c

780

if (i < ARRAY_SIZE(opregion->acpi->cadl))

sys/dev/drm/i915/intel_pm.c

295

for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {

sys/dev/drm/i915/intel_pm.c

7819

for (i = 0; i < ARRAY_SIZE(cparams); i++) {

sys/dev/drm/i915/intel_pm.c

9798

if (WARN_ON_ONCE(i >= ARRAY_SIZE(dev_priv->gt_pm.rc6.cur_residency)))

sys/dev/drm/i915/intel_runtime_pm.c

3048

ARRAY_SIZE(__power_well_descs))

sys/dev/drm/i915/intel_sdvo.c

2007

for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)

sys/dev/drm/i915/intel_sdvo.c

411

for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {

sys/dev/drm/i915/intel_sdvo.c

417

if (i == ARRAY_SIZE(sdvo_cmd_names)) {

sys/dev/drm/i915/intel_sdvo.c

66

#define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names)

sys/dev/drm/i915/intel_sprite.c

1801

num_plane_formats = ARRAY_SIZE(skl_planar_formats);

sys/dev/drm/i915/intel_sprite.c

1804

num_plane_formats = ARRAY_SIZE(skl_plane_formats);

sys/dev/drm/i915/intel_sprite.c

1821

num_plane_formats = ARRAY_SIZE(vlv_plane_formats);

sys/dev/drm/i915/intel_sprite.c

1833

num_plane_formats = ARRAY_SIZE(snb_plane_formats);

sys/dev/drm/i915/intel_sprite.c

1847

num_plane_formats = ARRAY_SIZE(snb_plane_formats);

sys/dev/drm/i915/intel_sprite.c

1852

num_plane_formats = ARRAY_SIZE(g4x_plane_formats);

sys/dev/drm/i915/intel_tv.c

1241

for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {

sys/dev/drm/i915/intel_tv.c

1334

for (j = 0; j < ARRAY_SIZE(input_res_table);

sys/dev/drm/i915/intel_tv.c

1441

const char *tv_format_names[ARRAY_SIZE(tv_modes)];

sys/dev/drm/i915/intel_tv.c

1540

for (i = 0; i < ARRAY_SIZE(tv_modes); i++)

sys/dev/drm/i915/intel_tv.c

1543

ARRAY_SIZE(tv_modes),

sys/dev/drm/i915/intel_uncore.c

1522

dev_priv->uncore.fw_domains_table_entries = ARRAY_SIZE((d)); \

sys/dev/drm/i915/intel_uncore.c

1678

remain = ARRAY_SIZE(reg_read_whitelist);

sys/dev/drm/i915/intel_uncore.c

51

BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);

sys/dev/drm/i915/intel_uncore.c

952

return BSEARCH(offset, regs, ARRAY_SIZE(gen##x##_shadowed_regs), \

sys/dev/drm/i915/vlv_dsi_pll.c

308

for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) {

sys/dev/drm/i915/vlv_dsi_pll.c

313

if (i == ARRAY_SIZE(lfsr_converts)) {

sys/dev/drm/include/drm/drm_connector.h

1339

for ((__i) = 0; (__i) < ARRAY_SIZE((connector)->encoder_ids) && \

sys/dev/drm/include/drm/drm_mode_object.h

110

for (i = 0; i < ARRAY_SIZE(list); i++) { \

sys/dev/drm/linux_list_sort.c

75

for (logn = 0; logn < ARRAY_SIZE(accum); logn++)

sys/dev/drm/linux_list_sort.c

90

KKASSERT((logn + 1) < ARRAY_SIZE(accum));

sys/dev/drm/radeon/atombios_dp.c

327

for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {

sys/dev/drm/radeon/btc_dpm.c

1248

num_blacklist_clocks = ARRAY_SIZE(btc_blacklist_clocks);

sys/dev/drm/radeon/btc_dpm.c

2698

rdev->pm.dpm.dyn_state.valid_sclk_values.count = ARRAY_SIZE(btc_valid_sclk);

sys/dev/drm/radeon/cayman_blit_shaders.c

320

const u32 cayman_default_size = ARRAY_SIZE(cayman_default_state);

sys/dev/drm/radeon/cik.c

1620

(const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init));

sys/dev/drm/radeon/cik.c

1623

(const u32)ARRAY_SIZE(bonaire_golden_registers));

sys/dev/drm/radeon/cik.c

1626

(const u32)ARRAY_SIZE(bonaire_golden_common_registers));

sys/dev/drm/radeon/cik.c

1629

(const u32)ARRAY_SIZE(bonaire_golden_spm_registers));

sys/dev/drm/radeon/cik.c

1634

(const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));

sys/dev/drm/radeon/cik.c

1637

(const u32)ARRAY_SIZE(kalindi_golden_registers));

sys/dev/drm/radeon/cik.c

1640

(const u32)ARRAY_SIZE(kalindi_golden_common_registers));

sys/dev/drm/radeon/cik.c

1643

(const u32)ARRAY_SIZE(kalindi_golden_spm_registers));

sys/dev/drm/radeon/cik.c

1648

(const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));

sys/dev/drm/radeon/cik.c

1651

(const u32)ARRAY_SIZE(godavari_golden_registers));

sys/dev/drm/radeon/cik.c

1654

(const u32)ARRAY_SIZE(kalindi_golden_common_registers));

sys/dev/drm/radeon/cik.c

1657

(const u32)ARRAY_SIZE(kalindi_golden_spm_registers));

sys/dev/drm/radeon/cik.c

1662

(const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init));

sys/dev/drm/radeon/cik.c

1665

(const u32)ARRAY_SIZE(spectre_golden_registers));

sys/dev/drm/radeon/cik.c

1668

(const u32)ARRAY_SIZE(spectre_golden_common_registers));

sys/dev/drm/radeon/cik.c

1671

(const u32)ARRAY_SIZE(spectre_golden_spm_registers));

sys/dev/drm/radeon/cik.c

1676

(const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init));

sys/dev/drm/radeon/cik.c

1679

(const u32)ARRAY_SIZE(hawaii_golden_registers));

sys/dev/drm/radeon/cik.c

1682

(const u32)ARRAY_SIZE(hawaii_golden_common_registers));

sys/dev/drm/radeon/cik.c

1685

(const u32)ARRAY_SIZE(hawaii_golden_spm_registers));

sys/dev/drm/radeon/cik.c

2350

ARRAY_SIZE(rdev->config.cik.tile_mode_array);

sys/dev/drm/radeon/cik.c

2352

ARRAY_SIZE(rdev->config.cik.macrotile_mode_array);

sys/dev/drm/radeon/cik.c

6152

for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {

sys/dev/drm/radeon/cik.c

6169

for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {

sys/dev/drm/radeon/cik.c

8343

(u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);

sys/dev/drm/radeon/cik.c

8347

(u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);

sys/dev/drm/radeon/cik_blit_shaders.c

246

const u32 cik_default_size = ARRAY_SIZE(cik_default_state);

sys/dev/drm/radeon/dce3_1_afmt.c

92

for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {

sys/dev/drm/radeon/dce6_afmt.c

240

for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {

sys/dev/drm/radeon/evergreen.c

1000

(const u32)ARRAY_SIZE(evergreen_golden_registers));

sys/dev/drm/radeon/evergreen.c

1003

(const u32)ARRAY_SIZE(evergreen_golden_registers2));

sys/dev/drm/radeon/evergreen.c

1006

(const u32)ARRAY_SIZE(juniper_mgcg_init));

sys/dev/drm/radeon/evergreen.c

1011

(const u32)ARRAY_SIZE(evergreen_golden_registers));

sys/dev/drm/radeon/evergreen.c

1014

(const u32)ARRAY_SIZE(evergreen_golden_registers2));

sys/dev/drm/radeon/evergreen.c

1017

(const u32)ARRAY_SIZE(redwood_mgcg_init));

sys/dev/drm/radeon/evergreen.c

1022

(const u32)ARRAY_SIZE(cedar_golden_registers));

sys/dev/drm/radeon/evergreen.c

1025

(const u32)ARRAY_SIZE(evergreen_golden_registers2));

sys/dev/drm/radeon/evergreen.c

1028

(const u32)ARRAY_SIZE(cedar_mgcg_init));

sys/dev/drm/radeon/evergreen.c

1033

(const u32)ARRAY_SIZE(wrestler_golden_registers));

sys/dev/drm/radeon/evergreen.c

1038

(const u32)ARRAY_SIZE(supersumo_golden_registers));

sys/dev/drm/radeon/evergreen.c

1043

(const u32)ARRAY_SIZE(supersumo_golden_registers));

sys/dev/drm/radeon/evergreen.c

1046

(const u32)ARRAY_SIZE(sumo_golden_registers));

sys/dev/drm/radeon/evergreen.c

1051

(const u32)ARRAY_SIZE(barts_golden_registers));

sys/dev/drm/radeon/evergreen.c

1056

(const u32)ARRAY_SIZE(turks_golden_registers));

sys/dev/drm/radeon/evergreen.c

1061

(const u32)ARRAY_SIZE(caicos_golden_registers));

sys/dev/drm/radeon/evergreen.c

2561

for (i = 0; i < ARRAY_SIZE(ni_dig_offsets); i++) {

sys/dev/drm/radeon/evergreen.c

2575

for (i = 0; i < ARRAY_SIZE(ni_dig_offsets); i++) {

sys/dev/drm/radeon/evergreen.c

2613

if (dig_fe >= ARRAY_SIZE(evergreen_dp_offsets)) {

sys/dev/drm/radeon/evergreen.c

5019

(u32)ARRAY_SIZE(sumo_rlc_save_restore_register_list);

sys/dev/drm/radeon/evergreen.c

989

(const u32)ARRAY_SIZE(evergreen_golden_registers));

sys/dev/drm/radeon/evergreen.c

992

(const u32)ARRAY_SIZE(evergreen_golden_registers2));

sys/dev/drm/radeon/evergreen.c

995

(const u32)ARRAY_SIZE(cypress_mgcg_init));

sys/dev/drm/radeon/evergreen_blit_shaders.c

303

const u32 evergreen_default_size = ARRAY_SIZE(evergreen_default_state);

sys/dev/drm/radeon/evergreen_cs.c

2690

BUILD_BUG_ON(ARRAY_SIZE(cayman_reg_safe_bm) != REG_SAFE_BM_SIZE);

sys/dev/drm/radeon/evergreen_cs.c

2691

BUILD_BUG_ON(ARRAY_SIZE(evergreen_reg_safe_bm) != REG_SAFE_BM_SIZE);

sys/dev/drm/radeon/evergreen_cs.c

38

#define REG_SAFE_BM_SIZE ARRAY_SIZE(evergreen_reg_safe_bm)

sys/dev/drm/radeon/evergreen_hdmi.c

188

for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {

sys/dev/drm/radeon/ni.c

2202

(u32)ARRAY_SIZE(tn_rlc_save_restore_register_list);

sys/dev/drm/radeon/ni.c

440

(const u32)ARRAY_SIZE(cayman_golden_registers));

sys/dev/drm/radeon/ni.c

443

(const u32)ARRAY_SIZE(cayman_golden_registers2));

sys/dev/drm/radeon/ni.c

467

(const u32)ARRAY_SIZE(dvst_golden_registers));

sys/dev/drm/radeon/ni.c

470

(const u32)ARRAY_SIZE(dvst_golden_registers2));

sys/dev/drm/radeon/ni.c

474

(const u32)ARRAY_SIZE(scrapper_golden_registers));

sys/dev/drm/radeon/ni.c

477

(const u32)ARRAY_SIZE(dvst_golden_registers2));

sys/dev/drm/radeon/ni_dpm.c

4197

rdev->pm.dpm.dyn_state.valid_sclk_values.count = ARRAY_SIZE(btc_valid_sclk);

sys/dev/drm/radeon/r100.c

2920

rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);

sys/dev/drm/radeon/r100.c

2923

rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);

sys/dev/drm/radeon/r200.c

549

rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm);

sys/dev/drm/radeon/r300.c

1317

rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);

sys/dev/drm/radeon/r420.c

81

rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);

sys/dev/drm/radeon/r600.c

4379

return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));

sys/dev/drm/radeon/r600_blit_shaders.c

716

const u32 r6xx_ps_size = ARRAY_SIZE(r6xx_ps);

sys/dev/drm/radeon/r600_blit_shaders.c

717

const u32 r6xx_vs_size = ARRAY_SIZE(r6xx_vs);

sys/dev/drm/radeon/r600_blit_shaders.c

718

const u32 r6xx_default_size = ARRAY_SIZE(r6xx_default_state);

sys/dev/drm/radeon/r600_blit_shaders.c

719

const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state);

sys/dev/drm/radeon/r600_cs.c

1615

if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {

sys/dev/drm/radeon/r600_cs.c

180

if (format >= ARRAY_SIZE(color_formats_table))

sys/dev/drm/radeon/r600_cs.c

191

if (format >= ARRAY_SIZE(color_formats_table))

sys/dev/drm/radeon/r600_cs.c

205

if (format >= ARRAY_SIZE(color_formats_table))

sys/dev/drm/radeon/r600_cs.c

215

if (format >= ARRAY_SIZE(color_formats_table))

sys/dev/drm/radeon/r600_cs.c

229

if (format >= ARRAY_SIZE(color_formats_table))

sys/dev/drm/radeon/r600_cs.c

977

if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {

sys/dev/drm/radeon/radeon_atombios.c

2100

(power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {

sys/dev/drm/radeon/radeon_atombios.c

2346

} else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {

sys/dev/drm/radeon/radeon_audio.c

617

for (i = 0; i < ARRAY_SIZE(hdmi_predefined_acr); i++)

sys/dev/drm/radeon/radeon_display.c

1408

sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);

sys/dev/drm/radeon/radeon_display.c

1422

sz = ARRAY_SIZE(radeon_tv_std_enum_list);

sys/dev/drm/radeon/radeon_display.c

1428

sz = ARRAY_SIZE(radeon_underscan_enum_list);

sys/dev/drm/radeon/radeon_display.c

1446

sz = ARRAY_SIZE(radeon_audio_enum_list);

sys/dev/drm/radeon/radeon_display.c

1452

sz = ARRAY_SIZE(radeon_dither_enum_list);

sys/dev/drm/radeon/radeon_display.c

1458

sz = ARRAY_SIZE(radeon_output_csc_enum_list);

sys/dev/drm/radeon/radeon_display.c

1526

BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));

sys/dev/drm/radeon/radeon_kms.c

923

int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms);

sys/dev/drm/radeon/radeon_legacy_tv.c

232

#define N_AVAILABLE_MODES ARRAY_SIZE(available_tv_modes)

sys/dev/drm/radeon/radeon_legacy_tv.c

647

for (i = 0; i < ARRAY_SIZE(SLOPE_limit); ++i) {

sys/dev/drm/radeon/radeon_pm.c

2008

return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));

sys/dev/drm/radeon/radeon_ring.c

543

for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) {

sys/dev/drm/radeon/radeon_ttm.c

1201

count = ARRAY_SIZE(radeon_ttm_debugfs_list);

sys/dev/drm/radeon/rs600.c

948

rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);

sys/dev/drm/radeon/rv515.c

608

rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);

sys/dev/drm/radeon/rv770.c

719

(const u32)ARRAY_SIZE(r7xx_golden_registers));

sys/dev/drm/radeon/rv770.c

722

(const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));

sys/dev/drm/radeon/rv770.c

726

(const u32)ARRAY_SIZE(rv770ce_golden_registers));

sys/dev/drm/radeon/rv770.c

730

(const u32)ARRAY_SIZE(rv770_golden_registers));

sys/dev/drm/radeon/rv770.c

733

(const u32)ARRAY_SIZE(rv770_mgcg_init));

sys/dev/drm/radeon/rv770.c

738

(const u32)ARRAY_SIZE(r7xx_golden_registers));

sys/dev/drm/radeon/rv770.c

741

(const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));

sys/dev/drm/radeon/rv770.c

744

(const u32)ARRAY_SIZE(rv730_golden_registers));

sys/dev/drm/radeon/rv770.c

747

(const u32)ARRAY_SIZE(rv730_mgcg_init));

sys/dev/drm/radeon/rv770.c

752

(const u32)ARRAY_SIZE(r7xx_golden_registers));

sys/dev/drm/radeon/rv770.c

755

(const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));

sys/dev/drm/radeon/rv770.c

758

(const u32)ARRAY_SIZE(rv710_golden_registers));

sys/dev/drm/radeon/rv770.c

761

(const u32)ARRAY_SIZE(rv710_mgcg_init));

sys/dev/drm/radeon/rv770.c

766

(const u32)ARRAY_SIZE(rv740_golden_registers));

sys/dev/drm/radeon/rv770.c

769

(const u32)ARRAY_SIZE(rv740_mgcg_init));

sys/dev/drm/radeon/si.c

1225

(const u32)ARRAY_SIZE(tahiti_golden_registers));

sys/dev/drm/radeon/si.c

1228

(const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));

sys/dev/drm/radeon/si.c

1231

(const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));

sys/dev/drm/radeon/si.c

1234

(const u32)ARRAY_SIZE(tahiti_golden_registers2));

sys/dev/drm/radeon/si.c

1239

(const u32)ARRAY_SIZE(pitcairn_golden_registers));

sys/dev/drm/radeon/si.c

1242

(const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));

sys/dev/drm/radeon/si.c

1245

(const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));

sys/dev/drm/radeon/si.c

1250

(const u32)ARRAY_SIZE(verde_golden_registers));

sys/dev/drm/radeon/si.c

1253

(const u32)ARRAY_SIZE(verde_golden_rlc_registers));

sys/dev/drm/radeon/si.c

1256

(const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));

sys/dev/drm/radeon/si.c

1259

(const u32)ARRAY_SIZE(verde_pg_init));

sys/dev/drm/radeon/si.c

1264

(const u32)ARRAY_SIZE(oland_golden_registers));

sys/dev/drm/radeon/si.c

1267

(const u32)ARRAY_SIZE(oland_golden_rlc_registers));

sys/dev/drm/radeon/si.c

1270

(const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));

sys/dev/drm/radeon/si.c

1275

(const u32)ARRAY_SIZE(hainan_golden_registers));

sys/dev/drm/radeon/si.c

1278

(const u32)ARRAY_SIZE(hainan_golden_registers2));

sys/dev/drm/radeon/si.c

1281

(const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init));

sys/dev/drm/radeon/si.c

2483

ARRAY_SIZE(rdev->config.si.tile_mode_array);

sys/dev/drm/radeon/si.c

5488

for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {

sys/dev/drm/radeon/si.c

5505

for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {

sys/dev/drm/radeon/si.c

6632

(u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);

sys/dev/drm/radeon/si_blit_shaders.c

253

const u32 si_default_size = ARRAY_SIZE(si_default_state);

sys/dev/drm/ttm/ttm_page_alloc_dma.c

602

for (i = 0; i < ARRAY_SIZE(t); i++) {

sys/dev/netif/re/re.c

24945

ARRAY_SIZE(phy_mcu_ram_code_8125b_1)

sys/dev/netif/re/re.c

24964

ARRAY_SIZE(phy_mcu_ram_code_8125b_2)

sys/dev/netif/re/re.c

3337

for (i = 0; i < ARRAY_SIZE(mcu_patch_code_8125a_2); i++) {

sys/dev/netif/re/re.c

3376

for (i = 0; i < ARRAY_SIZE(mcu_patch_code_8125b_2); i++) {

sys/dev/netif/re/re.h

1256

#ifndef ARRAY_SIZE

test/illumos/oclo/oclo.c

1302

for (size_t i = 0; i < ARRAY_SIZE(oclo_create); i++) {

test/illumos/oclo/oclo.c

88

error = sysctl(name, ARRAY_SIZE(name), pathname, &len, NULL, 0);