Symbol: HDMI_VBI_PACKET_CONTROL
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1577
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1610
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1611
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1612
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1619
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1652
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1653
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1654
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c
634
REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
140
SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
141
SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
142
SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
673
uint32_t HDMI_VBI_PACKET_CONTROL;
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
74
SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
567
REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
142
uint32_t HDMI_VBI_PACKET_CONTROL;
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
64
SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \
sys/dev/drm/radeon/evergreen_hdmi.c
331
WREG32(HDMI_VBI_PACKET_CONTROL + offset,