sys/dev/drm/amd/amdgpu/dce_v10_0.c

1629

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1707

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1671

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1749

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

644

REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

758

REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

145

SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

153

SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

672

uint32_t HDMI_INFOFRAME_CONTROL1;

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

73

SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

577

REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

141

uint32_t HDMI_INFOFRAME_CONTROL1;

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

63

SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \

sys/dev/drm/radeon/evergreen_hdmi.c

237

WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,