sys/dev/drm/amd/amdgpu/dce_v10_0.c

1617

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1619

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1701

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1703

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1659

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1661

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1743

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1745

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

640

REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

754

REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

762

REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

143

SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

151

SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

152

SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

671

uint32_t HDMI_INFOFRAME_CONTROL0;

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

72

SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

573

REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

140

uint32_t HDMI_INFOFRAME_CONTROL0;

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

62

SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \

sys/dev/drm/radeon/evergreen_hdmi.c

438

WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,

sys/dev/drm/radeon/evergreen_hdmi.c

446

WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,

sys/dev/drm/radeon/evergreen_hdmi.c

455

WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0);