sys/dev/drm/amd/amdgpu/dce_v10_0.c

1589

tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1590

tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1595

tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1596

tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1601

tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1602

tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1631

tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1632

tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1637

tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1638

tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1643

tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1644

tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

562

REG_UPDATE_3(HDMI_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

567

REG_UPDATE_5(HDMI_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

577

REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

581

REG_UPDATE_2(HDMI_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

585

REG_UPDATE_2(HDMI_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

592

REG_UPDATE_2(HDMI_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

596

REG_UPDATE_2(HDMI_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

602

REG_UPDATE_2(HDMI_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

616

REG_UPDATE_2(HDMI_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

628

REG_UPDATE_2(HDMI_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

136

SE_SF(HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

137

SE_SF(HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

138

SE_SF(HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

139

SE_SF(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

300

SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

301

SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

310

SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

311

SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

665

uint32_t HDMI_CONTROL;

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

68

SRI(HDMI_CONTROL, DIG, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

501

REG_UPDATE_5(HDMI_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

511

REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

515

REG_UPDATE_2(HDMI_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

519

REG_UPDATE_2(HDMI_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

526

REG_UPDATE_2(HDMI_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

530

REG_UPDATE_2(HDMI_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

536

REG_UPDATE_2(HDMI_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

549

REG_UPDATE_2(HDMI_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

561

REG_UPDATE_2(HDMI_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

132

uint32_t HDMI_CONTROL;

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

55

SRI(HDMI_CONTROL, DIG, id), \

sys/dev/drm/radeon/evergreen_hdmi.c

345

val = RREG32(HDMI_CONTROL + offset);

sys/dev/drm/radeon/evergreen_hdmi.c

372

WREG32(HDMI_CONTROL + offset, val);