Symbol: HDMI_ACR_PACKET_CONTROL
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1649
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1652
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1654
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1691
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1694
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1696
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c
1368
REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
178
SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
179
SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
180
SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
675
uint32_t HDMI_ACR_PACKET_CONTROL;
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
76
SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
1201
REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
144
uint32_t HDMI_ACR_PACKET_CONTROL;
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
66
SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
sys/dev/drm/radeon/evergreen_hdmi.c
85
WREG32(HDMI_ACR_PACKET_CONTROL + offset,
sys/dev/drm/radeon/evergreen_hdmi.c
88
WREG32(HDMI_ACR_PACKET_CONTROL + offset,