sys/dev/drm/amd/amdgpu/sdma_v2_4.c

389

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

391

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

986

tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

993

tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

624

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

626

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

670

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

768

temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);

sys/dev/misc/kbd/kbd.c

1381

case HALT: case PDWN:

sys/dev/misc/syscons/syscons.c

3986

case HALT:

usr.sbin/kbdcontrol/kbdcontrol.c

207

return HALT | 0x100;

usr.sbin/kbdcontrol/kbdcontrol.c

441

case HALT | 0x100:

usr.sbin/kbdcontrol/kbdcontrol.c

640

case HALT: