sys/dev/drm/i915/i915_irq.c

1468

if (gt_iir & GT_RENDER_USER_INTERRUPT)

sys/dev/drm/i915/i915_irq.c

1477

if (gt_iir & GT_RENDER_USER_INTERRUPT)

sys/dev/drm/i915/i915_irq.c

1501

if (iir & GT_RENDER_USER_INTERRUPT) {

sys/dev/drm/i915/i915_irq.c

4018

gt_irqs |= GT_RENDER_USER_INTERRUPT;

sys/dev/drm/i915/i915_irq.c

4144

GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |

sys/dev/drm/i915/i915_irq.c

4146

GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |

sys/dev/drm/i915/i915_irq.c

4148

GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |

sys/dev/drm/i915/i915_irq.c

4150

GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |

sys/dev/drm/i915/i915_irq.c

4153

GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |

sys/dev/drm/i915/i915_irq.c

4260

const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;

sys/dev/drm/i915/intel_guc_submission.c

1186

irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |

sys/dev/drm/i915/intel_guc_submission.c

1187

GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;

sys/dev/drm/i915/intel_lrc.c

2399

engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;

sys/dev/drm/i915/intel_ringbuffer.c

2258

engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;