sys/dev/drm/i915/intel_pm.c

1042

dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12;

sys/dev/drm/i915/intel_pm.c

1080

case G4X_WM_LEVEL_SR:

sys/dev/drm/i915/intel_pm.c

1177

level = max(level, G4X_WM_LEVEL_SR);

sys/dev/drm/i915/intel_pm.c

1252

crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],

sys/dev/drm/i915/intel_pm.c

1257

crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc,

sys/dev/drm/i915/intel_pm.c

1296

if (level <= G4X_WM_LEVEL_SR) {

sys/dev/drm/i915/intel_pm.c

1349

level = G4X_WM_LEVEL_SR;

sys/dev/drm/i915/intel_pm.c

1390

if (level >= G4X_WM_LEVEL_SR &&

sys/dev/drm/i915/intel_pm.c

1391

wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR))

sys/dev/drm/i915/intel_pm.c

1451

g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_SR) ||

sys/dev/drm/i915/intel_pm.c

1453

g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_SR)) &&

sys/dev/drm/i915/intel_pm.c

5809

max_level = G4X_WM_LEVEL_SR;