sys/dev/drm/i915/intel_pm.c

1043

dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;

sys/dev/drm/i915/intel_pm.c

1045

dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL;

sys/dev/drm/i915/intel_pm.c

1082

case G4X_WM_LEVEL_HPLL:

sys/dev/drm/i915/intel_pm.c

1253

crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);

sys/dev/drm/i915/intel_pm.c

1258

crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);

sys/dev/drm/i915/intel_pm.c

1303

if (level <= G4X_WM_LEVEL_HPLL) {

sys/dev/drm/i915/intel_pm.c

1361

level = G4X_WM_LEVEL_HPLL;

sys/dev/drm/i915/intel_pm.c

1393

else if (level >= G4X_WM_LEVEL_HPLL &&

sys/dev/drm/i915/intel_pm.c

1394

wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL))

sys/dev/drm/i915/intel_pm.c

1456

g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_HPLL) ||

sys/dev/drm/i915/intel_pm.c

1458

g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_HPLL)) &&

sys/dev/drm/i915/intel_pm.c

5807

max_level = G4X_WM_LEVEL_HPLL;