sys/dev/drm/amd/display/dc/dce/dce_opp.c

387

FMT_PIXEL_ENCODING, 0,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

392

FMT_PIXEL_ENCODING, 0,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

397

FMT_PIXEL_ENCODING, 1,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

402

FMT_PIXEL_ENCODING, 2,

sys/dev/drm/amd/display/dc/dce/dce_opp.h

120

OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_opp.h

190

OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_opp.h

234

type FMT_PIXEL_ENCODING; \

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c

166

REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c

169

REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c

172

REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 2);

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.h

118

type FMT_PIXEL_ENCODING; \

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.h

81

OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh), \