Symbol: FMT_CONTROL
sys/dev/drm/amd/display/dc/dce/dce_opp.c
188
REG_UPDATE_2(FMT_CONTROL,
sys/dev/drm/amd/display/dc/dce/dce_opp.c
192
REG_UPDATE_2(FMT_CONTROL,
sys/dev/drm/amd/display/dc/dce/dce_opp.c
198
REG_UPDATE_2(FMT_CONTROL,
sys/dev/drm/amd/display/dc/dce/dce_opp.c
386
REG_UPDATE_3(FMT_CONTROL,
sys/dev/drm/amd/display/dc/dce/dce_opp.c
391
REG_UPDATE_2(FMT_CONTROL,
sys/dev/drm/amd/display/dc/dce/dce_opp.c
396
REG_UPDATE_2(FMT_CONTROL,
sys/dev/drm/amd/display/dc/dce/dce_opp.c
401
REG_UPDATE_3(FMT_CONTROL,
sys/dev/drm/amd/display/dc/dce/dce_opp.c
441
REG_UPDATE(FMT_CONTROL,
sys/dev/drm/amd/display/dc/dce/dce_opp.c
494
REG_UPDATE(FMT_CONTROL,
sys/dev/drm/amd/display/dc/dce/dce_opp.c
498
REG_WAIT(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, 1, 10, 10);
sys/dev/drm/amd/display/dc/dce/dce_opp.h
111
OPP_SF(FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_opp.h
120
OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_opp.h
121
OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_opp.h
122
OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh)
sys/dev/drm/amd/display/dc/dce/dce_opp.h
126
OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_opp.h
127
OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_opp.h
128
OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
sys/dev/drm/amd/display/dc/dce/dce_opp.h
132
OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_opp.h
133
OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_opp.h
134
OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
sys/dev/drm/amd/display/dc/dce/dce_opp.h
140
OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_opp.h
141
OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_opp.h
142
OPP_SF(FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_opp.h
143
OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_opp.h
144
OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_opp.h
145
OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
sys/dev/drm/amd/display/dc/dce/dce_opp.h
250
uint32_t FMT_CONTROL;
sys/dev/drm/amd/display/dc/dce/dce_opp.h
46
SRI(FMT_CONTROL, FMT, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c
166
REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0);
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c
169
REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 1);
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c
172
REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 2);
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c
318
REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, 0);
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c
77
REG_UPDATE_2(FMT_CONTROL,
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c
81
REG_UPDATE_2(FMT_CONTROL,
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c
88
REG_UPDATE_2(FMT_CONTROL,
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.h
38
SRI(FMT_CONTROL, FMT, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.h
55
uint32_t FMT_CONTROL; \