sys/dev/drm/amd/amdgpu/dce_v10_0.c

524

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

525

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

526

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

527

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

529

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

530

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

536

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

537

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

538

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

539

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

540

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

542

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

543

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

549

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

550

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

551

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

552

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

553

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

555

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

556

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

550

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

551

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

552

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

553

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

555

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

556

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

562

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

563

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

564

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

565

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

566

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

568

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

569

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

575

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

576

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

577

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

578

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

579

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

581

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

582

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);

sys/dev/drm/amd/display/dc/dce/dce_opp.c

109

REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

118

REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

124

REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

134

REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

163

REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

168

REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

173

REG_UPDATE(FMT_BIT_DEPTH_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

235

REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

245

REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

267

REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

272

REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

276

REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

287

REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

302

REG_UPDATE(FMT_BIT_DEPTH_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

305

REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

311

REG_UPDATE(FMT_BIT_DEPTH_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_opp.h

103

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_opp.h

104

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_opp.h

105

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_opp.h

106

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_opp.h

107

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_opp.h

108

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_opp.h

109

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_opp.h

110

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_opp.h

249

uint32_t FMT_BIT_DEPTH_CONTROL;

sys/dev/drm/amd/display/dc/dce/dce_opp.h

45

SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \

sys/dev/drm/amd/display/dc/dce/dce_opp.h

90

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_opp.h

91

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_opp.h

92

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_opp.h

93

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_opp.h

94

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_opp.h

95

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_opp.h

96

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_opp.h

97

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_opp.h

98

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_opp.h

99

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c

121

REG_UPDATE_6(FMT_BIT_DEPTH_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c

53

REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c

64

REG_UPDATE_7(FMT_BIT_DEPTH_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.h

37

SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.h

54

uint32_t FMT_BIT_DEPTH_CONTROL; \

sys/dev/drm/radeon/cik.c

8818

WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/evergreen.c

1330

WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/r600.c

336

WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);