sys/dev/drm/radeon/evergreen.c

1369

if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN))

sys/dev/drm/radeon/evergreen.c

1664

tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);

sys/dev/drm/radeon/evergreen.c

1666

WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/evergreen.c

1689

tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);

sys/dev/drm/radeon/evergreen.c

1691

WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/evergreen.c

2661

crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;

sys/dev/drm/radeon/evergreen.c

2674

tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);

sys/dev/drm/radeon/evergreen.c

2679

WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);

sys/dev/drm/radeon/evergreen.c

2703

tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);

sys/dev/drm/radeon/evergreen.c

2705

WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);

sys/dev/drm/radeon/evergreen.c

2809

tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);

sys/dev/drm/radeon/evergreen.c

2812

WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);

sys/dev/drm/radeon/evergreen.c

3786

if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN) {

sys/dev/drm/radeon/radeon_device.c

673

reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |

sys/dev/drm/radeon/radeon_device.c

674

RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);

sys/dev/drm/radeon/radeon_device.c

676

reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |

sys/dev/drm/radeon/radeon_device.c

677

RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);

sys/dev/drm/radeon/radeon_device.c

680

reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |

sys/dev/drm/radeon/radeon_device.c

681

RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);