sys/dev/drm/radeon/atombios_crtc.c

2233

radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;

sys/dev/drm/radeon/cik.c

6916

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

6929

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

7268

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);

sys/dev/drm/radeon/cik.c

7286

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,

sys/dev/drm/radeon/cik.c

7338

EVERGREEN_CRTC5_REGISTER_OFFSET);

sys/dev/drm/radeon/cik.c

7378

WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET,

sys/dev/drm/radeon/cik.c

7385

WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);

sys/dev/drm/radeon/cik.c

7387

WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);

sys/dev/drm/radeon/evergreen.c

118

EVERGREEN_CRTC5_REGISTER_OFFSET

sys/dev/drm/radeon/evergreen_cs.c

1032

EVERGREEN_VLINE_START_END + EVERGREEN_CRTC5_REGISTER_OFFSET

sys/dev/drm/radeon/evergreen_cs.c

1040

EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET

sys/dev/drm/radeon/radeon_device.c

681

RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);

sys/dev/drm/radeon/radeon_display.c

1506

EVERGREEN_CRTC5_REGISTER_OFFSET,

sys/dev/drm/radeon/radeon_display.c

1864

EVERGREEN_CRTC5_REGISTER_OFFSET);

sys/dev/drm/radeon/radeon_display.c

1866

EVERGREEN_CRTC5_REGISTER_OFFSET);

sys/dev/drm/radeon/radeon_dp_mst.c

19

EVERGREEN_CRTC5_REGISTER_OFFSET,

sys/dev/drm/radeon/si.c

139

EVERGREEN_CRTC5_REGISTER_OFFSET