sys/dev/drm/radeon/atombios_crtc.c

2230

radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;

sys/dev/drm/radeon/cik.c

6915

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

6928

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

7267

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);

sys/dev/drm/radeon/cik.c

7284

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,

sys/dev/drm/radeon/cik.c

7336

EVERGREEN_CRTC4_REGISTER_OFFSET);

sys/dev/drm/radeon/cik.c

7375

WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,

sys/dev/drm/radeon/cik.c

7381

WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);

sys/dev/drm/radeon/cik.c

7383

WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);

sys/dev/drm/radeon/evergreen.c

117

EVERGREEN_CRTC4_REGISTER_OFFSET,

sys/dev/drm/radeon/evergreen_cs.c

1031

EVERGREEN_VLINE_START_END + EVERGREEN_CRTC4_REGISTER_OFFSET,

sys/dev/drm/radeon/evergreen_cs.c

1039

EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,

sys/dev/drm/radeon/radeon_device.c

680

reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |

sys/dev/drm/radeon/radeon_display.c

1505

EVERGREEN_CRTC4_REGISTER_OFFSET,

sys/dev/drm/radeon/radeon_display.c

1857

EVERGREEN_CRTC4_REGISTER_OFFSET);

sys/dev/drm/radeon/radeon_display.c

1859

EVERGREEN_CRTC4_REGISTER_OFFSET);

sys/dev/drm/radeon/radeon_dp_mst.c

18

EVERGREEN_CRTC4_REGISTER_OFFSET,

sys/dev/drm/radeon/si.c

138

EVERGREEN_CRTC4_REGISTER_OFFSET,