sys/dev/drm/radeon/atombios_crtc.c

2227

radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;

sys/dev/drm/radeon/cik.c

6912

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

6925

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

7264

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);

sys/dev/drm/radeon/cik.c

7280

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,

sys/dev/drm/radeon/cik.c

7332

EVERGREEN_CRTC3_REGISTER_OFFSET);

sys/dev/drm/radeon/cik.c

7361

WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET,

sys/dev/drm/radeon/cik.c

7368

WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);

sys/dev/drm/radeon/cik.c

7370

WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);

sys/dev/drm/radeon/evergreen.c

116

EVERGREEN_CRTC3_REGISTER_OFFSET,

sys/dev/drm/radeon/evergreen_cs.c

1030

EVERGREEN_VLINE_START_END + EVERGREEN_CRTC3_REGISTER_OFFSET,

sys/dev/drm/radeon/evergreen_cs.c

1038

EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET,

sys/dev/drm/radeon/radeon_device.c

677

RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);

sys/dev/drm/radeon/radeon_display.c

1504

EVERGREEN_CRTC3_REGISTER_OFFSET,

sys/dev/drm/radeon/radeon_display.c

1850

EVERGREEN_CRTC3_REGISTER_OFFSET);

sys/dev/drm/radeon/radeon_display.c

1852

EVERGREEN_CRTC3_REGISTER_OFFSET);

sys/dev/drm/radeon/radeon_dp_mst.c

17

EVERGREEN_CRTC3_REGISTER_OFFSET,

sys/dev/drm/radeon/si.c

137

EVERGREEN_CRTC3_REGISTER_OFFSET,