sys/dev/drm/radeon/atombios_crtc.c

2224

radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;

sys/dev/drm/radeon/cik.c

6911

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

6924

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

7263

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);

sys/dev/drm/radeon/cik.c

7278

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,

sys/dev/drm/radeon/cik.c

7330

EVERGREEN_CRTC2_REGISTER_OFFSET);

sys/dev/drm/radeon/cik.c

7358

WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET,

sys/dev/drm/radeon/cik.c

7364

WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);

sys/dev/drm/radeon/cik.c

7366

WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);

sys/dev/drm/radeon/evergreen.c

115

EVERGREEN_CRTC2_REGISTER_OFFSET,

sys/dev/drm/radeon/evergreen_cs.c

1029

EVERGREEN_VLINE_START_END + EVERGREEN_CRTC2_REGISTER_OFFSET,

sys/dev/drm/radeon/evergreen_cs.c

1037

EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET,

sys/dev/drm/radeon/radeon_device.c

676

reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |

sys/dev/drm/radeon/radeon_display.c

1503

EVERGREEN_CRTC2_REGISTER_OFFSET,

sys/dev/drm/radeon/radeon_display.c

1843

EVERGREEN_CRTC2_REGISTER_OFFSET);

sys/dev/drm/radeon/radeon_display.c

1845

EVERGREEN_CRTC2_REGISTER_OFFSET);

sys/dev/drm/radeon/radeon_dp_mst.c

16

EVERGREEN_CRTC2_REGISTER_OFFSET,

sys/dev/drm/radeon/si.c

136

EVERGREEN_CRTC2_REGISTER_OFFSET,