sys/dev/drm/radeon/atombios_crtc.c

2221

radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;

sys/dev/drm/radeon/cik.c

6909

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

6921

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

7261

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);

sys/dev/drm/radeon/cik.c

7274

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,

sys/dev/drm/radeon/cik.c

7327

EVERGREEN_CRTC1_REGISTER_OFFSET);

sys/dev/drm/radeon/cik.c

7345

WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET,

sys/dev/drm/radeon/cik.c

7352

WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);

sys/dev/drm/radeon/cik.c

7354

WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);

sys/dev/drm/radeon/evergreen.c

114

EVERGREEN_CRTC1_REGISTER_OFFSET,

sys/dev/drm/radeon/evergreen_cs.c

1028

EVERGREEN_VLINE_START_END + EVERGREEN_CRTC1_REGISTER_OFFSET,

sys/dev/drm/radeon/evergreen_cs.c

1036

EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET,

sys/dev/drm/radeon/radeon_device.c

674

RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);

sys/dev/drm/radeon/radeon_display.c

1502

EVERGREEN_CRTC1_REGISTER_OFFSET,

sys/dev/drm/radeon/radeon_display.c

1836

EVERGREEN_CRTC1_REGISTER_OFFSET);

sys/dev/drm/radeon/radeon_display.c

1838

EVERGREEN_CRTC1_REGISTER_OFFSET);

sys/dev/drm/radeon/radeon_dp_mst.c

15

EVERGREEN_CRTC1_REGISTER_OFFSET,

sys/dev/drm/radeon/si.c

135

EVERGREEN_CRTC1_REGISTER_OFFSET,