sys/dev/drm/radeon/atombios_crtc.c

2218

radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;

sys/dev/drm/radeon/cik.c

6908

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

6920

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

7260

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);

sys/dev/drm/radeon/cik.c

7272

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,

sys/dev/drm/radeon/cik.c

7325

EVERGREEN_CRTC0_REGISTER_OFFSET);

sys/dev/drm/radeon/cik.c

7342

WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,

sys/dev/drm/radeon/cik.c

7348

WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);

sys/dev/drm/radeon/cik.c

7350

WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);

sys/dev/drm/radeon/evergreen.c

113

EVERGREEN_CRTC0_REGISTER_OFFSET,

sys/dev/drm/radeon/evergreen_cs.c

1027

EVERGREEN_VLINE_START_END + EVERGREEN_CRTC0_REGISTER_OFFSET,

sys/dev/drm/radeon/evergreen_cs.c

1035

EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,

sys/dev/drm/radeon/radeon_device.c

673

reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |

sys/dev/drm/radeon/radeon_display.c

1501

EVERGREEN_CRTC0_REGISTER_OFFSET,

sys/dev/drm/radeon/radeon_display.c

1829

EVERGREEN_CRTC0_REGISTER_OFFSET);

sys/dev/drm/radeon/radeon_display.c

1831

EVERGREEN_CRTC0_REGISTER_OFFSET);

sys/dev/drm/radeon/radeon_dp_mst.c

14

static const int offsets[] = { EVERGREEN_CRTC0_REGISTER_OFFSET,

sys/dev/drm/radeon/si.c

134

EVERGREEN_CRTC0_REGISTER_OFFSET,