Symbol: ENABLE_L1_TLB
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
116
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
296
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
621
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
742
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
848
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
986
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
136
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
328
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
451
type ENABLE_L1_TLB;\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c
780
ENABLE_L1_TLB, 1,
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
381
HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
572
type ENABLE_L1_TLB;\
sys/dev/drm/radeon/cik.c
5459
ENABLE_L1_TLB |
sys/dev/drm/radeon/evergreen.c
2398
tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
sys/dev/drm/radeon/evergreen.c
2481
tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
sys/dev/drm/radeon/ni.c
1298
ENABLE_L1_TLB |
sys/dev/drm/radeon/r600.c
1139
tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
sys/dev/drm/radeon/r600.c
1231
tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
sys/dev/drm/radeon/rv770.c
909
tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
sys/dev/drm/radeon/rv770.c
986
tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
sys/dev/drm/radeon/si.c
4285
ENABLE_L1_TLB |