sys/dev/drm/amd/amdgpu/cz_ih.c

63

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);

sys/dev/drm/amd/amdgpu/cz_ih.c

83

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);

sys/dev/drm/amd/amdgpu/iceland_ih.c

63

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);

sys/dev/drm/amd/amdgpu/iceland_ih.c

83

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);

sys/dev/drm/amd/amdgpu/tonga_ih.c

63

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);

sys/dev/drm/amd/amdgpu/tonga_ih.c

80

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);

sys/dev/drm/amd/amdgpu/vega10_ih.c

50

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);

sys/dev/drm/amd/amdgpu/vega10_ih.c

67

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);

sys/dev/drm/radeon/cik.c

6844

ih_cntl |= ENABLE_INTR;

sys/dev/drm/radeon/cik.c

6864

ih_cntl &= ~ENABLE_INTR;

sys/dev/drm/radeon/r600.c

3609

ih_cntl |= ENABLE_INTR;

sys/dev/drm/radeon/r600.c

3622

ih_cntl &= ~ENABLE_INTR;

sys/dev/drm/radeon/si.c

5911

ih_cntl |= ENABLE_INTR;

sys/dev/drm/radeon/si.c

5924

ih_cntl &= ~ENABLE_INTR;