sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

459

ENABLE, 1);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

568

ENABLE, 1);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

703

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

705

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

722

ENABLE, 1);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

726

ENABLE, 0);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

743

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

747

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);

sys/dev/drm/amd/amdgpu/tonga_ih.c

155

ENABLE, 1);

sys/dev/drm/amd/amdgpu/tonga_ih.c

158

ENABLE, 0);

sys/dev/drm/amd/amdgpu/vega10_ih.c

143

ENABLE, 1);

sys/dev/drm/amd/amdgpu/vega10_ih.c

146

ENABLE, 0);

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

1723

if (psr_configuration.bits.ENABLE) {

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

613

ENABLE, eanble);

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

643

ENABLE, eanble);

sys/dev/drm/amd/display/dc/dce/dce_mem_input.h

311

type ENABLE; /* MC_HUB_RDREQ_DMIF_LIMIT */\

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

492

.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

497

.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

507

.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

512

.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

607

.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

612

.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK

sys/dev/drm/amd/display/dc/inc/hw/link_encoder.h

73

unsigned char ENABLE : 1;