sys/dev/drm/amd/amdgpu/amdgpu_object.c

1110

AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1873

pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1963

if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1966

bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1967

bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1968

mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1969

tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1970

num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1983

} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1915

pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2005

if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2008

bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2009

bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2010

mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2011

tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2012

num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2025

} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1802

pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1884

if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1887

bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1888

bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1889

mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1890

tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1891

num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1900

} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2367

if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2370

bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2371

bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2372

mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2373

tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2374

num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2386

} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2392

AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2412

AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);