sys/dev/drm/i915/intel_display.c

15555

WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);

sys/dev/drm/i915/intel_display.c

15556

WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);

sys/dev/drm/i915/intel_display.c

15557

WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);

sys/dev/drm/i915/intel_display.c

16339

error->plane[i].control = I915_READ(DSPCNTR(i));

sys/dev/drm/i915/intel_display.c

3402

i915_reg_t reg = DSPCNTR(i9xx_plane);

sys/dev/drm/i915/intel_display.c

3466

I915_WRITE_FW(DSPCNTR(i9xx_plane), 0);

sys/dev/drm/i915/intel_display.c

3471

POSTING_READ_FW(DSPCNTR(i9xx_plane));

sys/dev/drm/i915/intel_display.c

3494

val = I915_READ(DSPCNTR(i9xx_plane));

sys/dev/drm/i915/intel_display.c

7879

val = I915_READ(DSPCNTR(i9xx_plane));

sys/dev/drm/i915/intel_pm.c

8491

I915_WRITE(DSPCNTR(pipe),

sys/dev/drm/i915/intel_pm.c

8492

I915_READ(DSPCNTR(pipe)) |

sys/dev/drm/i915/vlv_dsi.c

1700

val = I915_READ(DSPCNTR(i9xx_plane));