sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1119

uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1135

dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1137

dpcd_addr = DP_SINK_COUNT_ESI;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

43

#define SIDE_BAND_MSG(address) (address >= DP_SIDEBAND_MSG_DOWN_REQ_BASE && address < DP_SINK_COUNT_ESI)

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

1669

uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

1673

DP_SINK_COUNT_ESI,

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

1680

irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

1681

irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

1682

irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

1683

irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

1684

irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

1685

irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];

sys/dev/drm/i915/intel_dp.c

4085

return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,

sys/dev/drm/i915/intel_dp.c

4312

DP_SINK_COUNT_ESI+1,

sys/dev/drm/radeon/radeon_dp_mst.c

717

DP_SINK_COUNT_ESI, esi, 8);

sys/dev/drm/radeon/radeon_dp_mst.c

727

DP_SINK_COUNT_ESI + 1, &esi[1], 3);

sys/dev/drm/radeon/radeon_dp_mst.c

733

DP_SINK_COUNT_ESI, esi, 8);